专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

WO02091616A3 ELECTROMAGNETICALLY COUPLED INTERCONNECT SYSTEM ARCHITECTURE 审中-公开
标题翻译：电磁耦合互联系统架构
公开(公告)号：WO02091616A3
公开(公告)日：2003-03-27
申请号：PCT/US0147114
申请日：2001-11-13
申请人： FORMFACTOR INC , MILLER CHARLES A
发明人： MILLER CHARLES A
IPC分类号： H04B5/02 , H04B5/00 , G06F13/40
CPC分类号： H04B5/0012 , H01L23/48 , H01L2924/0002 , H01L2924/3011 , H04B5/0075 , H04B5/02 , H05K1/141 , H05K1/181 , H05K3/366 , H05K2201/10098 , Y02P70/611 , H01L2924/00
摘要： An electromagnetic interconnect method and apparatus effects contactless, proximity connections between elements in an electronics system. Data to be communicated between elements in an electronic system are modulated into a carrier signal and transmitted contactlessly by electromagnetic coupling. The electromagnetic coupling may be directly between elements in the system or through an intermediary transmission medium.
摘要翻译：电磁互连方法和装置实现电子系统中元件之间的非接触式接近连接。要在电子系统中的元件之间传送的数据被调制成载波信号并通过电磁耦合非接触地传输。电磁耦合可以直接在系统中的元件之间或通过中间传输介质。

22. 发明申请

WO2006029340A3 METHOD AND APPARATUS FOR REMOTELY BUFFERING TEST CHANNELS 审中-公开
标题翻译：用于远程缓冲测试通道的方法和设备
公开(公告)号：WO2006029340A3
公开(公告)日：2007-07-26
申请号：PCT/US2005032202
申请日：2005-09-08
申请人： FORMFACTOR INC , MILLER CHARLES A
发明人： MILLER CHARLES A
IPC分类号： G01R31/28
CPC分类号： G01R31/3008
摘要： A system is provided to enable leakage current measurement or parametric tests to be performed with an isolation buffer provided in a channel line. Multiple such isolation buffers are used to connect a single signal channel to multiple lines. Leakage current measurement is provided by providing a buffer bypass element, such as a resistor or transmission gate, between the input and output of each buffer. The buffer bypass element can be used to calibrate buffer delay out of the test system by using TDR measurements to determine the buffer delay based on reflected pulses through the buffer bypass element. Buffer delay can likewise be calibrated out by comparing measurements of a buffered and non-buffered channel line, or by measuring a device having a known delay.
摘要翻译：提供了一种系统，用于使泄漏电流测量或参数测试能够与通道线中提供的隔离缓冲器一起进行。多个这样的隔离缓冲器用于将单个信号通道连接到多条线路。泄漏电流测量通过在每个缓冲器的输入和输出之间提供缓冲旁路元件（例如电阻器或传输门）来提供。缓冲旁路元件可用于通过使用TDR测量来确定缓冲器延迟，以通过缓冲旁路元件反射的脉冲来校准测试系统中的缓冲延迟。同样可以通过比较缓冲和非缓冲通道线的测量值，或通过测量具有已知延迟的器件来校准缓冲器延迟。

23. 发明申请

WO2005106763A3 METHOD AND APPARATUS FOR CALIBRATING COMMUNICATIONS CHANNELS 审中-公开
标题翻译：用于校准通信信道的方法和装置
公开(公告)号：WO2005106763A3
公开(公告)日：2006-05-18
申请号：PCT/US2005012649
申请日：2005-04-15
申请人： FORMFACTOR INC , MILLER CHARLES A
发明人： MILLER CHARLES A
IPC分类号： H04B17/00 , G06F19/00
CPC分类号： H04B17/0085 , H04B17/21 , H04B17/26 , H04B17/364
摘要： A periodic signal is driven onto a transmission line, and the frequency of the periodic signal is varied from an initial frequency that corresponds to a quarter wave or half wave of an estimated length of the transmission line. A null or a peak in the envelope of the voltage or current wave induced on the transmission line by the periodic signal is detected at or near the end of the transmission line onto which the signal is driven. The frequency of the periodic signal that caused the null or peak may be used to calculated the length of the transmission line or a propagation delay through the transmission line. A plurality of transmission lines may be deskewed by determining the propagation delay through each transmission line and adjusting a variable delay in each transmission line so that the transmissions lines approximately equal overall propagation delays.
摘要翻译：周期信号被驱动到传输线上，并且周期信号的频率从对应于传输线估计长度的四分之一波或半波的初始频率变化。在信号被驱动的传输线的末端处或附近，检测在周期信号在传输线上感应的电压或电流波的包络中的零点或峰值。导致零或峰值的周期信号的频率可用于计算传输线的长度或通过传输线的传播延迟。多个传输线可以通过确定通过每个传输线的传播延迟并调整每个传输线中的可变延迟使得传输线近似等于总体传播延迟而进行偏斜校正。

24. 发明申请

WO03030255A2 MULTIPLE DIE INTERCONNECT SYSTEM 审中-公开
标题翻译：多个DIE互连系统
公开(公告)号：WO03030255A2
公开(公告)日：2003-04-10
申请号：PCT/US0231856
申请日：2002-10-03
申请人： FORMFACTOR INC , MILLER CHARLES A
发明人： MILLER CHARLES A
IPC分类号： H01L25/18 , H01L23/13 , H01L23/498 , H01L23/538 , H01L25/065 , H01L25/07 , H05K7/10 , H01L21/98
CPC分类号： H01L23/13 , H01L23/49811 , H01L23/5385 , H01L25/0652 , H01L2224/05571 , H01L2224/05573 , H01L2224/1134 , H01L2224/13099 , H01L2224/16 , H01L2224/16225 , H01L2924/00013 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/15312 , H01L2924/1532 , H01L2924/16152 , H01L2924/19107 , H01L2924/3011 , H05K7/1092 , Y10T29/49126 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/53174 , Y10T29/53178 , H01L2224/05599
摘要： A multiple integrated circuit (IC) die assembly includes a base IC die and secondary IC dice mounted on a surface of the base IC die. A set of protruding contacts formed on the surface of the base IC die and extending beyond the secondary IC dice link the surface of the base IC die to a printed circuit board (PCB) substrate with the secondary IC die residing between the base IC die and the PCB substrate.
摘要翻译：多集成电路（IC）模具组件包括安装在基底IC芯片的表面上的基底IC芯片和次级IC芯片。形成在基底IC芯片的表面上并延伸超过次级IC芯片的一组突出接点将基底IC芯片的表面连接到印刷电路板（PCB）基板，其中第二IC芯片位于基底IC芯片和 PCB基板。

25. 发明申请

WO02078083A3 IN-STREET INTEGRATED CIRCUIT WAFER VIA 审中-公开
标题翻译： IN-STREET集成电路通过
公开(公告)号：WO02078083A3
公开(公告)日：2003-03-20
申请号：PCT/US0208540
申请日：2002-03-19
申请人： FORMFACTOR INC , MILLER CHARLES A
发明人： MILLER CHARLES A
IPC分类号： H01L21/768 , H01L23/498 , H01L25/065 , H01L23/485
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/49805 , H01L25/0657 , H01L2224/02371 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , Y10T29/49155 , Y10T29/49165 , H01L2224/05599
摘要： Vertical holes (156) are created in streets separating individual integrated circuit (IC) dies formed on a semiconductor wafer, the holes spanning saw-lines (154) along which the wafer is to be later cut to separate the IC die from one another to form individual IC chips. The holes are then filled with conductive material (165). After the wafer is cut along the saw-lines, portions of the conductive material (165) on opposing sides of the saw-lines remain on peripheral edges of the IC chip to form signal paths (174, 180, 270, 272) between the upper and lower surfaces of the IC chips.
摘要翻译：在形成在半导体晶片上的各个集成电路（IC）晶片的街道上形成垂直孔（156），穿过锯切线（154）的孔，晶片将沿着该切割线切割以将IC管芯彼此分离以分离形成单个IC芯片。然后用导电材料（165）填充孔。在沿着锯线切割晶片之后，在锯片的相对侧上的导电材料（165）的部分保留在IC芯片的周边边缘上，以形成信号路径（174,180,270,272） IC芯片的上表面和下表面。

26. 发明申请

WO0163672A3 INTEGRATED CIRCUIT INTERCONNECT SYSTEM HAVING MATCHED IMPEDANCE AND CAPACITANCE 审中-公开
标题翻译：具有匹配阻抗和电容的集成电路互连系统
公开(公告)号：WO0163672A3
公开(公告)日：2002-04-18
申请号：PCT/US0105970
申请日：2001-02-21
申请人： FORMFACTOR INC , MILLER CHARLES A
发明人： MILLER CHARLES A
IPC分类号： H01L23/522 , H01L23/60 , H01L23/62 , H01L27/02 , H01L23/66
CPC分类号： H01L23/522 , H01L23/5227 , H01L23/60 , H01L23/62 , H01L24/48 , H01L24/49 , H01L27/0248 , H01L2223/6611 , H01L2224/48091 , H01L2224/4813 , H01L2224/49113 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01033 , H01L2924/01043 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： In an interconnect system for providing access to a common I/O terminal for multiple circuit devices such as drivers, receivers and electrostatic discharge (ESD) protection devices implemented on an IC, each such device is provided with a separate contact pad within the IC. The contact pads (82A, 82B) are linked to one another and to the IC I/O terminal though inductive conductors such as bond wires (88A, 88B), metalization layer traces in the IC, or legs of a forked, lithographically-defined spring contact formed on the IC. The conductor inductance isolates the capacitance of the circuit devices from one another, thereby improving characteristics of the frequency response of the interconnect system. Also the ESD protection function is distributed among multiple ESD devices interconnected by series inductors to provide a multi-pole filter at each IC terminal. The inductances of the conductors and various capacitances of the interconnect system are also appropriately adjusted to optimize desired interconnect system frequency response characteristics.
摘要翻译：在用于提供对诸如在IC上实现的驱动器，接收器和静电放电（ESD））保护装置的多个电路装置的公共I / O端子的接入的互连系统中，每个这样的装置在IC内设置有单独的接触焊盘。接触焊盘（82A，82B）通过诸如接合线（88A，88B）的感应导体，IC中的金属化层迹线或叉形，光刻定义的接触焊盘（82A，82B）彼此连接并连接到IC I / O端子 IC上形成弹簧触点。导体电感将电路器件的电容彼此隔离，从而提高互连系统的频率响应特性。此外，ESD保护功能分布在由串联电感器互连的多个ESD器件中，以在每个IC端子处提供多极滤波器。还可以适当地调整互连系统的导体和各种电容的电感以优化所需的互连系统频率响应特性。

27. 发明专利

JP2002174669A SIMULTANEOUS TEST FOR INTEGRATED CIRCUIT DEVICE, USING INTER-DUT COMPARISON AND INTRA-DUT COMARISON 审中-公开
公开(公告)号：JP2002174669A
公开(公告)日：2002-06-21
申请号：JP2001296088
申请日：2001-09-27
申请人： FORMFACTOR INC
发明人： ROY RICHARD S , MILLER CHARLES A
IPC分类号： G01R31/28 , G01R31/319 , G01R31/3193 , G11C29/48 , G11C29/56 , H01L21/66 , G11C29/00
摘要： PROBLEM TO BE SOLVED: To provide a means for testing a plurality of integrated circuit devices at the same time. SOLUTION: This system for testing the plurality of integrated circuit(IC) devices (DUT) of testing objects is provided with an interface circuit coupled to a tester to receives a data value from a single channel or a plurality of channels so as to provide error information as to the DUT. The interface circuit transmits the data value (received from the tester via the single channel) to the plurality of DUTs. The interface circuit conducts comarison using the data value read from the DUT, and generates an error value for showing a comarison result in response thereto. The error value is returned to the tester via the same channel or a different channel.

28. 发明专利

JP2009124714A Electromagnetically coupled interconnect system architecture 审中-公开
标题翻译：电磁耦合互联系统架构
公开(公告)号：JP2009124714A
公开(公告)日：2009-06-04
申请号：JP2008321499
申请日：2008-12-17
申请人： Formfactor Inc , フォームファクター, インコーポレイテッド
发明人： MILLER CHARLES A
IPC分类号： H04B5/02 , H01L25/04 , H01L25/18 , H04B5/00
CPC分类号： H04B5/0012 , H01L23/48 , H01L2924/0002 , H01L2924/3011 , H04B5/0075 , H04B5/02 , H05K1/141 , H05K1/181 , H05K3/366 , H05K2201/10098 , Y02P70/611 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide contactless and proximity connections small in signal distortion and attenuation between elements in an electronics system. SOLUTION: The electronics system includes a transmission line, and a plurality of electronic components each having an electromagnetic coupler. Data to be communicated between the elements in the electronics system are modulated into a carrier signal and transmitted contactlessly by electromagnetic coupling. The electromagnetic coupling may be present directly between the elements in the system or through an intermediary transmission medium. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供电子系统中元件之间的信号失真和衰减小的非接触式和接近连接。解决方案：电子系统包括传输线和多个电子部件，每个电子部件均具有电磁耦合器。要在电子系统中的元件之间通信的数据被调制成载波信号并通过电磁耦合非接触地传送。电磁耦合可以直接存在于系统中的元件之间或通过中间传输介质。版权所有（C）2009，JPO＆INPIT

29. 发明专利

JP2012189607A Apparatus for increasing operating frequency of system for testing electronic devices 审中-公开
标题翻译：增加用于测试电子设备的系统的操作频率的装置
公开(公告)号：JP2012189607A
公开(公告)日：2012-10-04
申请号：JP2012119406
申请日：2012-05-25
申请人： Formfactor Inc , フォームファクター, インコーポレイテッド
发明人： MILLER CHARLES A
IPC分类号： G01R31/28 , H01L21/66
CPC分类号： G01R31/2889 , G01R31/31905
摘要： PROBLEM TO BE SOLVED: To increase a frequency with which a DUT can be tested.SOLUTION: A test system comprises communication channels 220 and 222 of which terminals are in probes 110d and 110e which have contact with input terminals 208 and 210 of an electronic device 112 to be tested. Resistors are connected between grounds and the communications channel 220 and 222 near the probes. The resistors reduce input resistance of the terminals and thereby reduce rise and fall times of the input terminals 208 and 210. Shut resistors 402 and 404 are provided in each branch, which reduces input resistance of the terminals, and thereby reduces rise and fall times of the input terminals 208 and 210. The shunt resistors 402 and 404 may also be sized to reduce, minimize, or eliminate signal reflection retracing the channel.
摘要翻译：要解决的问题：增加可以测试DUT的频率。解决方案：测试系统包括通信信道220和222，其中终端处于与要测试的电子设备112的输入端子208和210接触的探针110d和110e中。电阻器连接在探头附近的接地和通信通道220和222之间。电阻器降低端子的输入电阻，从而减少输入端子208和210的上升和下降时间。在每个分支中设置闭合电阻器402和404，这降低了端子的输入电阻，从而减少了上升和下降时间输入端子208和210.分流电阻器402和404也可以被设计成减小，最小化或消除信道反射回波信道。版权所有（C）2013，JPO＆INPIT

30. 发明专利

DE60234014D1 未知
公开(公告)号：DE60234014D1
公开(公告)日：2009-11-26
申请号：DE60234014
申请日：2002-01-15
申请人： FORMFACTOR INC
发明人： HREISH EMAD B , MILLER CHARLES A
IPC分类号： H03H7/075 , H05K1/02 , H01P1/04 , H03H7/01 , H03H7/38 , H05K1/11 , H05K1/16 , H05K3/34 , H05K3/42
摘要： A printed circuit board (PCB) via, providing a conductor extending vertically between microstrip or stripline conductors formed on separate layers of a PCB, includes a conductive pad surrounding the conductor and embedded within the PCB between those PCB layers. The pad's shunt capacitance and the magnitudes of capacitances of other portions of the via are sized relative to the conductor's inherent inductance to optimize frequency response characteristics of the via.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式