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21. 发明授权

US07714313B2 Resistive RAM having at least one varistor and methods of operating the same 有权
标题翻译：具有至少一个压敏电阻的电阻RAM及其操作方法
公开(公告)号：US07714313B2
公开(公告)日：2010-05-11
申请号：US11655086
申请日：2007-01-19
申请人： Jung-Hyun Lee , Eun-Hong Lee , Sang-Jun Choi , In-Kyeong Yoo , Myoung-Jae Lee
发明人： Jung-Hyun Lee , Eun-Hong Lee , Sang-Jun Choi , In-Kyeong Yoo , Myoung-Jae Lee
IPC分类号： H01L47/00
CPC分类号： G11C13/003 , G11C13/0007 , G11C2213/32 , G11C2213/76
摘要： Resistive memory devices having at least one varistor and methods of operating the same are disclosed. The resistive memory device may include at least one bottom electrode line, at least one top electrode line crossing the at least one bottom electrode line, and at least one stack structure disposed at an intersection of the at least one top electrode line and the at least one bottom electrode line including a varistor and a data storage layer.
摘要翻译：公开了具有至少一个压敏电阻的电阻式存储器件及其操作方法。电阻式存储器件可以包括至少一个底部电极线，与至少一个底部电极线交叉的至少一个顶部电极线以及至少一个堆叠结构，该至少一个堆叠结构设置在至少一个顶部电极线和至少一个顶部电极线的交点处一个底部电极线包括变阻器和数据存储层。

22. 发明授权

US07498600B2 Variable resistance random access memory device and a method of fabricating the same 有权
标题翻译：可变电阻随机存取存储器件及其制造方法
公开(公告)号：US07498600B2
公开(公告)日：2009-03-03
申请号：US11702623
申请日：2007-02-06
申请人： Choong-Rae Cho , Eun-Hong Lee , Stefanovich Genrikh , El Mostafa Bourim
发明人： Choong-Rae Cho , Eun-Hong Lee , Stefanovich Genrikh , El Mostafa Bourim
IPC分类号： H01L29/02 , G11C11/56
CPC分类号： H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/146 , Y10S438/90
摘要： Provided is a variable resistance random access memory device having an n+ interfacial layer and a method of fabricating the same. The variable resistance random access memory device may include a lower electrode, an n+ interfacial layer on the lower electrode, a buffer layer on the n+ interfacial layer, an oxide layer on the buffer layer and having a variable resistance characteristic and an upper electrode on the oxide layer.
摘要翻译：提供了具有n +界面层的可变电阻随机存取存储器件及其制造方法。可变电阻随机存取存储器件可以包括下电极，下电极上的n +界面层，n +界面层上的缓冲层，缓冲层上的氧化物层和可变电阻特性上的上电极氧化层。

23. 发明授权

US07491987B2 Junction field effect thin film transistor 有权
标题翻译：结场效应薄膜晶体管
公开(公告)号：US07491987B2
公开(公告)日：2009-02-17
申请号：US11705108
申请日：2007-02-12
申请人： Stefanovich Genrikh , Choong-Rae Cho , Eun-Hong Lee
发明人： Stefanovich Genrikh , Choong-Rae Cho , Eun-Hong Lee
IPC分类号： H01L29/80
CPC分类号： H01L29/8086 , H01L29/66901
摘要： Example embodiments are directed to a junction field effect thin film transistor (JFETFT) including a first electrode formed on a substrate, a first conductive first gate semiconductor pattern formed on the first gate electrode, a second conductive semiconductor channel layer formed on the substrate and the first conductive first gate semiconductor pattern, and source and drain electrodes formed on the second conductive semiconductor pattern and located at both sides of the first conductive gate semiconductor pattern. The JFETFT may further include a first conductive second gate semiconductor pattern formed on a portion of the second conductive semiconductor channel layer between the source electrode and the drain electrode, and a second gate electrode formed on the first conductive second gate semiconductor pattern.
摘要翻译：示例性实施例涉及一种结型场效应薄膜晶体管（JFETFT），其包括形成在衬底上的第一电极，形成在第一栅电极上的第一导电第一栅极半导体图案，形成在衬底上的第二导电半导体沟道层和第一导电第一栅极半导体图案，以及形成在第二导电半导体图案上并位于第一导电栅极半导体图案的两侧的源极和漏极。 JFETFT还可以包括形成在源电极和漏极之间的第二导电半导体沟道层的一部分上的第一导电第二栅极半导体图案，以及形成在第一导电第二栅极半导体图案上的第二栅电极。

24. 发明授权

US07436704B2 Non-volatile memory devices and method thereof 有权
标题翻译：非易失性存储器件及其方法
公开(公告)号：US07436704B2
公开(公告)日：2008-10-14
申请号：US11490129
申请日：2006-07-21
申请人： Won-Joo Kim , Sung-Jae Byun , Yoon-Dong Park , Eun-Hong Lee , Suk-Pil Kim , Jae-Woong Hyun
发明人： Won-Joo Kim , Sung-Jae Byun , Yoon-Dong Park , Eun-Hong Lee , Suk-Pil Kim , Jae-Woong Hyun
IPC分类号： G11C11/34
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C16/0416 , G11C2213/31 , G11C2213/32 , G11C2213/72 , H01L27/11521 , H01L27/11568
摘要： Non-volatile memory devices and a method thereof are provided. A non-volatile memory device according to an example embodiment of the present invention may include a first transistor including a source, a drain, and a control gate, a first storage node coupled to the first transistor, the first storage node configured to store information in a first manner, a first diode having a first end connected to the source of the transistor, the first diode configured to rectify a flow of current from the source of the transistor and a second storage node connected to a second end of the first diode, the second storage node configured to store information in a second manner. Another non-volatile memory device according to another example embodiment of the present invention may include a semiconductor substrate having a first conductivity type including an active region defined by a device isolating layer, a source region and a drain region formed by doping an impurity having a second conductivity type in the active region, a control gate electrode insulated from the active region, the control gate electrode extending across the active region disposed between the source region and the drain region, a first storage node layer interposed between the active region and the control gate electrode configured to store information in a first manner, a second storage node layer disposed on the source region configured to store information in a second manner and a diode interposed between the source region and the second storage node layer to rectify a flow of current to the source region. The example method may be directed to obtaining a higher storage capacity per cell area in either of the above-described example non-volatile memory devices.
摘要翻译：提供了非易失性存储器件及其方法。根据本发明的示例性实施例的非易失性存储器件可以包括：第一晶体管，包括源极，漏极和控制栅极;耦合到第一晶体管的第一存储节点，第一存储节点，被配置为存储信息以第一方式，第一二极管具有连接到晶体管的源极的第一端，第一二极管被配置为对来自晶体管的源极的电流进行整流，以及连接到第一二极管的第二端的第二存储节点所述第二存储节点被配置为以第二方式存储信息。根据本发明的另一示例性实施例的另一非易失性存储器件可以包括具有第一导电类型的半导体衬底，该第一导电类型包括由器件隔离层限定的有源区，源区和漏区，有源区中的第二导电类型，与有源区绝缘的控制栅电极，跨越设置在源区和漏区之间的有源区延伸的控制栅电极，插入在有源区和控制区之间的第一存储节点层栅电极，其被配置为以第一方式存储信息;第二存储节点层，被布置在源区域上，被配置为以第二方式存储信息;以及二极管，插入在源区域和第二存储节点层之间，以将电流流向源区域。示例性方法可以针对在上述任一示例非易失性存储器件中获得每个单元区域的更高的存储容量。

25. 发明申请

US20080001184A1 Junction field effect thin film transistor 有权
标题翻译：结场效应薄膜晶体管
公开(公告)号：US20080001184A1
公开(公告)日：2008-01-03
申请号：US11705108
申请日：2007-02-12
申请人： Stefanovich Genrikh , Choong-Rae Cho , Eun-Hong Lee
发明人： Stefanovich Genrikh , Choong-Rae Cho , Eun-Hong Lee
IPC分类号： H01L29/80
CPC分类号： H01L29/8086 , H01L29/66901
摘要： Example embodiments are directed to a junction field effect thin film transistor (JFETFT) including a first electrode formed on a substrate, a first conductive first gate semiconductor pattern formed on the first gate electrode, a second conductive semiconductor channel layer formed on the substrate and the first conductive first gate semiconductor pattern, and source and drain electrodes formed on the second conductive semiconductor pattern and located at both sides of the first conductive gate semiconductor pattern. The JFETFT may further include a first conductive second gate semiconductor pattern formed on a portion of the second conductive semiconductor channel layer between the source electrode and the drain electrode, and a second gate electrode formed on the first conductive second gate semiconductor pattern.
摘要翻译：示例性实施例涉及一种结型场效应薄膜晶体管（JFETFT），其包括形成在衬底上的第一电极，形成在第一栅电极上的第一导电第一栅极半导体图案，形成在衬底上的第二导电半导体沟道层和第一导电第一栅极半导体图案，以及形成在第二导电半导体图案上并位于第一导电栅极半导体图案的两侧的源极和漏极。 JFETFT还可以包括形成在源电极和漏极之间的第二导电半导体沟道层的一部分上的第一导电第二栅极半导体图案，以及形成在第一导电第二栅极半导体图案上的第二栅电极。

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