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21. 发明授权

US09252270B2 Floating body cell 有权
标题翻译：浮体细胞
公开(公告)号：US09252270B2
公开(公告)日：2016-02-02
申请号：US13713393
申请日：2012-12-13
申请人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/78 , H01L29/786 , H01L29/66
CPC分类号： H01L29/7841 , H01L29/66545 , H01L29/78654
摘要： Methods of forming a floating body cell (FBC) with faster programming and lower refresh rate and the resulting devices are disclosed. Embodiments include forming a silicon on insulator (SOI) layer on a substrate; forming a band-engineered layer surrounding and/or on the SOI layer; forming a source region and a drain region with at least one of the source region and the drain region being on the band-engineered layer; and forming a gate on the SOI layer, between the source and drain regions.
摘要翻译：公开了具有更快编程和更低刷新率的浮体单元（FBC）的形成方法以及所得到的器件。实施例包括在基板上形成绝缘体上硅（SOI）层; 形成围绕和/或在SOI层上的带工程层; 形成源极区域和漏极区域，所述源极区域和漏极区域中的至少一个在所述带状工程化层上; 以及在SOI层上，在源区和漏区之间形成栅极。

22. 发明授权

US08895402B2 Fin-type memory 有权
标题翻译：鳍型记忆
公开(公告)号：US08895402B2
公开(公告)日：2014-11-25
申请号：US13602310
申请日：2012-09-03
申请人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
发明人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L21/20
CPC分类号： H01L45/1233 , H01L45/04 , H01L45/06 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/1675 , H01L45/1691
摘要： Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is less than a lithographic resolution. The fin stack layers are patterned using the spacers as a mask to form fin stacks. The fin stacks contact the bottom electrodes. An interlevel dielectric (ILD) layer is formed on the substrate. The ILD layer fills spaces around the fin stacks. An upper electrode level is formed on the ILD layer. The upper electrode level has top electrodes in contact with the fin stacks. The electrodes and fin stacks form fin-type memory cells.
摘要翻译：公开了用于形成装置的存储装置和方法。提供了制备具有与底部电极的较低电极电平的衬底。鳍状堆叠层形成在下部电极层上。垫片形成在翅片堆叠层的顶部。间隔物的宽度小于光刻分辨率。使用间隔件作为掩模来对翅片堆叠层进行图案化以形成翅片堆叠。鳍片堆叠接触底部电极。在衬底上形成层间电介质（ILD）层。 ILD层填充散热片堆叠周围的空间。在ILD层上形成上电极层。上电极电平具有与散热片堆叠接触的顶部电极。电极和散热片堆叠形成鳍式存储单元。

23. 发明申请

US20120223394A1 SELF-ALIGNED CONTACT FOR REPLACEMENT METAL GATE AND SILICIDE LAST PROCESSES 有权
标题翻译：用于替换金属门和硅化物最后工艺的自对准接触件
公开(公告)号：US20120223394A1
公开(公告)日：2012-09-06
申请号：US13041134
申请日：2011-03-04
申请人： Eng Huat Toh , Elgin Quek
发明人： Eng Huat Toh , Elgin Quek
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L27/088 , H01L21/28518 , H01L21/76801 , H01L21/76816 , H01L21/76834 , H01L21/76897 , H01L21/823475 , H01L29/78
摘要： A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches.
摘要翻译：高K /金属栅极半导体器件具有较大的自对准触点，电阻降低。实施例包括在源极/漏极区域之间的衬底上形成第一高k金属栅极堆叠，在STI区域上形成第二高k金属栅极堆叠以及在金属栅极堆叠之间形成第一ILD，形成蚀刻停止层和在衬底上顺序地具有第二ILD，在金属栅堆叠上的第二ILD中具有开口，在开口的边缘上形成间隔物，在第二ILD和间隔物上形成第三ILD，在源/漏区上去除第一ILD 在邻近间隔物的源极/漏极区域上以及在间隔物的一部分上方去除蚀刻停止层，第二ILD和第三ILD，形成第一沟槽，在第二高k金属栅极上去除第三ILD 堆叠和一部分间隔物，形成第二沟槽，并在第一和第二沟槽中形成接触。

24. 发明授权

US09054209B2 Compact charge trap multi-time programmable memory 有权
标题翻译：紧凑型电荷阱多次可编程存储器
公开(公告)号：US09054209B2
公开(公告)日：2015-06-09
申请号：US13587072
申请日：2012-08-16
申请人： Eng Huat Toh , Khee Yong Lim , Shyue Seng Tan , Elgin Quek
发明人： Eng Huat Toh , Khee Yong Lim , Shyue Seng Tan , Elgin Quek
IPC分类号： H01L29/792 , H01L21/28 , H01L29/423 , H01L29/66
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/4234 , H01L29/66833
摘要： A method for enabling fabrication of memory devices requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: forming a gate stack on a substrate; forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack; forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack; forming a charge-trapping spacer on each tunnel oxide liner; and forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack.
摘要翻译：公开了一种能够制造不需要或最小的用于具有低成本，小占地面积和多次编程能力的制造的附加掩模的存储器件的方法。实施例包括：在基板上形成栅叠层; 在所述栅极堆叠的一侧上的所述衬底中形成源极延伸区域，其中在所述栅极叠层的另一侧上不形成漏极延伸区域; 在所述栅极堆叠的侧表面和所述栅极叠层的每一侧的所述衬底上形成隧道氧化物衬垫; 在每个隧道氧化物衬垫上形成电荷捕获间隔物; 以及在所述栅极堆叠的一侧上的所述衬底中形成源极以及在所述栅极叠层的另一侧上的所述衬底中的漏极。

25. 发明授权

US08698118B2 Compact RRAM device and methods of making same 有权
标题翻译：紧凑的RRAM设备及其制作方法
公开(公告)号：US08698118B2
公开(公告)日：2014-04-15
申请号：US13408221
申请日：2012-02-29
申请人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
发明人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L29/02 , H01L47/00 , H01L29/04 , H01L29/06
CPC分类号： H01L45/04 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/146 , H01L45/147
摘要： Disclosed herein is a compact RRAM (Resistance Random Access Memory) device structure and various methods of making such an RRAM device. In one example, a device disclosed herein includes a gate electrode, a conductive sidewall spacer and at least one variable resistance material layer positioned between the gate electrode and the conductive sidewall spacer.
摘要翻译：这里公开了紧凑的RRAM（电阻随机存取存储器）装置结构和制造这种RRAM装置的各种方法。在一个示例中，本文公开的器件包括栅极，导电侧壁隔离物和位于栅电极和导电侧壁间隔物之间的至少一个可变电阻材料层。

26. 发明授权

US08674332B2 RRAM device with an embedded selector structure and methods of making same 有权
标题翻译：具有嵌入式选择器结构的RRAM器件及其制作方法
公开(公告)号：US08674332B2
公开(公告)日：2014-03-18
申请号：US13445658
申请日：2012-04-12
申请人： Eng Huat Toh , Shyue Seng Tan , Elgin Quek
发明人： Eng Huat Toh , Shyue Seng Tan , Elgin Quek
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： H01L45/04 , H01L27/2445 , H01L27/2463 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1666
摘要： One device disclosed herein includes first and second sidewall spacers positioned above a semiconducting substrate, wherein the first and second sidewall spacers are comprised of at least a conductive material, a conductive word line electrode positioned between the first and second sidewall spacers and first and second regions of variable resistance material positioned between the conductive word line electrode and the conductive material of the first and second sidewall spacers, respectively. This example also includes a base region of a bipolar transistor in the substrate below the word line electrode, an emitter region formed below the base region and first and second collector regions formed in the substrate within the base region, wherein the first collector region is positioned at least partially under the first region of variable resistance material and the second collector region is positioned at least partially under the second region of variable resistance material.
摘要翻译：本文公开的一种装置包括位于半导体衬底之上的第一和第二侧壁间隔物，其中第一和第二侧壁间隔物由至少导电材料构成，位于第一和第二侧壁间隔物之间的导电字线电极和第一和第二区域分别位于导电字线电极和第一和第二侧壁间隔物的导电材料之间的可变电阻材料。该示例还包括在字线电极下方的基板中的双极晶体管的基极区域，形成在基极区域下方的发射极区域和形成在基极区域内的基板中的第一和第二集电极区域，其中第一集电极区域被定位至少部分地在可变电阻材料的第一区域下方，并且第二集电极区域至少部分地位于可变电阻材料的第二区域的下方。

27. 发明申请

US20140008713A1 METHOD AND APPARATUS FOR EMBEDDED NVM UTILIZING AN RMG PROCESS 有权
标题翻译：用于嵌入式NVM的方法和装置利用RMG过程
公开(公告)号：US20140008713A1
公开(公告)日：2014-01-09
申请号：US13543340
申请日：2012-07-06
申请人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
发明人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L21/8239 , H01L27/088
CPC分类号： H01L21/823437 , H01L21/28273 , H01L21/823425 , H01L21/823468 , H01L27/11524 , H01L29/66545
摘要： A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with RMG processes. Embodiments include forming a first and a second dual polysilicon gate-stack structure on an upper surface of a substrate, forming spacers on opposite sidewalls of each of the first and the second dual polysilicon gate-stack structures, forming an ILD adjacent to an exposed sidewall of each spacer, removing the first dual polysilicon gate-stack structure, forming a first cavity between the spacers, and forming a HKMG in the first cavity, wherein the HKMG forms an access gate.
摘要翻译：通过集成嵌入式非易失性存储器（eNVM）与RMG进程来制造存储器件。实施例包括在衬底的上表面上形成第一和第二双多晶硅栅叠层结构，在第一和第二双多晶硅栅叠层结构中的每一个的相对侧壁上形成间隔物，形成与露出侧壁相邻的ILD 移除所述第一双多晶硅栅堆叠结构，在所述间隔物之间形成第一空腔，并在所述第一空腔中形成HKMG，其中所述HKMG形成存取栅极。

28. 发明申请

US20130270501A1 RRAM DEVICE WITH AN EMBEDDED SELECTOR STRUCTURE AND METHODS OF MAKING SAME 有权
标题翻译：具有嵌入式选择器结构的RRAM器件及其制造方法
公开(公告)号：US20130270501A1
公开(公告)日：2013-10-17
申请号：US13445658
申请日：2012-04-12
申请人： Eng Huat Toh , Shyue Seng Tan , Elgin Quek
发明人： Eng Huat Toh , Shyue Seng Tan , Elgin Quek
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L45/04 , H01L27/2445 , H01L27/2463 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1666
摘要： One device disclosed herein includes first and second sidewall spacers positioned above a semiconducting substrate, wherein the first and second sidewall spacers are comprised of at least a conductive material, a conductive word line electrode positioned between the first and second sidewall spacers and first and second regions of variable resistance material positioned between the conductive word line electrode and the conductive material of the first and second sidewall spacers, respectively. This example also includes a base region of a bipolar transistor in the substrate below the word line electrode, an emitter region formed below the base region and first and second collector regions formed in the substrate within the base region, wherein the first collector region is positioned at least partially under the first region of variable resistance material and the second collector region is positioned at least partially under the second region of variable resistance material.
摘要翻译：本文公开的一种装置包括位于半导体衬底之上的第一和第二侧壁间隔物，其中第一和第二侧壁间隔物由至少导电材料构成，位于第一和第二侧壁间隔物之间的导电字线电极和第一和第二区域分别位于导电字线电极和第一和第二侧壁间隔物的导电材料之间的可变电阻材料。该示例还包括在字线电极下方的基板中的双极晶体管的基极区域，形成在基极区域下方的发射极区域和形成在基极区域内的基板中的第一和第二集电极区域，其中第一集电极区域被定位至少部分地在可变电阻材料的第一区域下方，并且第二集电极区域至少部分地位于可变电阻材料的第二区域的下方。

29. 发明申请

US20130240821A1 THREE DIMENSIONAL RRAM DEVICE, AND METHODS OF MAKING SAME 有权
标题翻译：三维RRAM装置及其制造方法
公开(公告)号：US20130240821A1
公开(公告)日：2013-09-19
申请号：US13423793
申请日：2012-03-19
申请人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
发明人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： H01L27/2409 , H01L27/2445 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： Disclosed herein are various embodiments of novel three dimensional RRAM devices, and various methods of making such devices. In one example, a device disclosed herein includes a first electrode for a first bit line comprising a variable resistance material, a second electrode for a second bit line comprising a variable resistance material and a third electrode positioned between the variable resistance material of the first bit line and the variable resistance material of the second bit line.
摘要翻译：本文公开了新型三维RRAM设备的各种实施例以及制造这些设备的各种方法。在一个示例中，本文公开的装置包括用于第一位线的第一电极，其包括可变电阻材料，用于第二位线的第二电极，包括可变电阻材料和位于第一位的可变电阻材料之间的第三电极线和第二位线的可变电阻材料。

30. 发明授权

US08368127B2 Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current 有权
标题翻译：制造具有高驱动电流的硅隧道场效应晶体管（TFET）的方法
公开(公告)号：US08368127B2
公开(公告)日：2013-02-05
申请号：US12587511
申请日：2009-10-08
申请人： Ming Zhu , Shyue Seng Tan , Eng Huat Toh , Elgin Quek
发明人： Ming Zhu , Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L29/76
CPC分类号： H01L21/26586 , B82Y10/00 , H01L29/0895 , H01L29/7391 , H01L29/7606 , H01L29/7613
摘要： A method (and semiconductor device) of fabricating a TFET device provides a source region having at least a portion thereof positioned underneath a gate dielectric. In one embodiment, the TFET includes an N+ drain region and a P+ source region in a silicon substrate, where the N+ drain region is silicon and the P+ source region is silicon germanium (SiGe). The source region includes a first region of a first type (e.g., P+ SiGe) and a second region of a second type (undoped SiGe), where at least a portion of the source region is positioned below the gate dielectric. This structure decreases the tunneling barrier width and increases drive current (Id).
摘要翻译：制造TFET器件的方法（和半导体器件）提供了一个源极区，其源极区至少有一部分位于栅极电介质的下面。在一个实施例中，TFET在硅衬底中包括N +漏极区域和P +源极区域，其中N +漏极区域是硅并且P +源极区域是硅锗（SiGe）。源区包括第一类型的第一区域（例如，P + SiGe）和第二类型（未掺杂的SiGe）的第二区域，其中源极区域的至少一部分位于栅极电介质的下方。该结构降低了隧道势垒宽度并增加了驱动电流（Id）。

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