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21. 发明授权

US08402422B2 Wiring design device, method and recording medium 有权
标题翻译：接线设计装置，方法和记录介质
公开(公告)号：US08402422B2
公开(公告)日：2013-03-19
申请号：US13048687
申请日：2011-03-15
申请人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Kazunori Kumagai
发明人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Kazunori Kumagai
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A wiring design device to conduct wiring design on a printed wiring board that includes a plurality of conductive layers, the wiring design device including: noise contaminating part extracting means for extracting a part in a condition where noise contaminates a signal, the part being on a wiring-designed line, based on a route of the line and a physical condition around the route; route modification processing means for modifying the route of the line by moving the extracted part on the line in the condition where noise contaminates the signal to a position that avoids the condition where noise contaminates the signal; and line length adjusting means for conducting a line length adjustment on the line to compensate for a variation of the line length of the line when the variation of the line length of the line occurs due to modifying the route of the line.
摘要翻译：一种布线设计装置，用于在包括多个导电层的印刷线路板上进行布线设计，所述布线设计装置包括：噪声污染部分提取装置，用于在噪声污染信号的情况下提取部分，所述部分在基于线路的路线和路线周围的物理条件进行布线设计的线路; 路线修改处理装置，用于通过在噪声污染信号的情况下将提取的部分移动到行上来修改行的路线到避免噪声污染信号的状况的位置; 以及线长调整装置，用于当线路的线路长度的变化由于改变线路的路线而发生时，进行线路上的线路长度调整以补偿线路的线路长度的变化。

22. 发明申请

US20110061039A1 CIRCUIT BOARD DESIGN AID APPARATUS, CIRCUIT BOARD DESIGN AID METHOD, AND COMPUTER-READABLE STORAGE MEDIUM STORTING CIRCUIT BOARD DESIGN AID PROGRAM 有权
标题翻译：电路板设计辅助设备，电路板设计辅助方法和计算机可读存储介质存储电路板设计辅助程序
公开(公告)号：US20110061039A1
公开(公告)日：2011-03-10
申请号：US12883445
申请日：2010-09-16
申请人： Kazunori KUMAGAI , Eiichi Konno
发明人： Kazunori KUMAGAI , Eiichi Konno
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , H05K1/0219 , H05K3/0005 , H05K2201/09618
摘要： The present disclosure includes a basic shield pattern element generation section configured to generate a basic shield pattern element based on a geometry of the pattern element and a preset pattern generation condition; a prohibition region generation section configured to generate a prohibition region based on a geometry of an element for which a clearance check is to be performed located around the wiring pattern and a clearance condition between the element for performing a clearance check and the wiring pattern; and a shield pattern geometry generation section configured to generate the shield pattern by excluding the geometry of the prohibition region from a geometry of the basic shield pattern element, thereby improving the design efficiency and design quality by efficiently generating shield patterns even when an element for which a clearance check is to be performed is present in the vicinity of the wiring pattern.
摘要翻译：本公开内容包括：基本屏蔽图案元素生成部，被配置为基于所述图案元素的几何形状和预设图案生成条件生成基本屏蔽图案元素; 禁止区域生成部，其被配置为基于在布线图案周围进行间隙检查的元件的几何形状以及用于进行间隙检查的元件与布线图案之间的间隙状态来生成禁止区域; 以及屏蔽图案几何生成部，被配置为通过从基本屏蔽图案元件的几何形状排除禁止区域的几何形状来生成屏蔽图案，从而通过有效地生成屏蔽图案来提高设计效率和设计质量，即使当其执行间隙检查存在于布线图案附近。

23. 发明申请

US20090125862A1 Wiring path information creating method and wiring path information creating apparatus 有权
标题翻译：布线路径信息生成方法和布线路径信息生成装置
公开(公告)号：US20090125862A1
公开(公告)日：2009-05-14
申请号：US12222661
申请日：2008-08-13
申请人： Yoshitaka Nishio , Eiichi Konno
发明人： Yoshitaka Nishio , Eiichi Konno
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A wiring processing apparatus decides each group formed by sorting signals that flow between component pins. Then, the wiring processing apparatus reads printed circuit board data and identifies a net cluster that belongs to each group. After a net cluster that belongs to each group is identified, the wiring processing apparatus refers to the printed circuit board data about the identified net cluster, and automatically creates each wiring route that indicates a wiring scanning area of the signal cluster in each group. Thus the wiring processing apparatus displays them on the printed board data. After the wiring route is automatically created, the wiring processing apparatus automatically creates wiring route information that corresponds to each wiring route, and controls them according to each wiring route.
摘要翻译：接线处理装置决定通过分配在分量引脚之间流动的信号而形成的每个组。然后，布线处理装置读取印刷电路板数据并识别属于每个组的网络簇。在识别属于每个组的网络集群之后，布线处理装置参考关于所识别的网络集群的印刷电路板数据，并且自动创建指示每个组中的信号簇的布线扫描区域的每个布线路线。因此，布线处理装置将它们显示在印刷电路板数据上。在自动生成布线路径之后，布线处理装置自动生成与各布线路线对应的布线路线信息，并根据各布线路进行控制。

24. 发明授权

US08856717B2 Shielded pattern generation for a circuit design board 有权
标题翻译：电路设计板的屏蔽图案生成
公开(公告)号：US08856717B2
公开(公告)日：2014-10-07
申请号：US12883445
申请日：2010-09-16
申请人： Kazunori Kumagai , Eiichi Konno
发明人： Kazunori Kumagai , Eiichi Konno
IPC分类号： G06F17/50 , H05K3/00 , H05K1/02
CPC分类号： G06F17/5077 , H05K1/0219 , H05K3/0005 , H05K2201/09618
摘要： A circuit board design aid is achieved by generating a shield pattern for a wiring pattern including a pattern element in a circuit board by increasing a width of a geometry of the pattern element by an amount corresponding to a shield pattern spacing set as a preset pattern generation condition. A prohibition region is generated based on a geometry of an element for which a clearance check is to be performed located around the wiring pattern and a clearance condition between the element for performing a clearance check and the wiring pattern. Then, the shield pattern is generated by excluding the geometry of the prohibition region from the geometry of the basic shield pattern element.
摘要翻译：电路板的设计辅助是通过增加图形元素的几何形状的宽度来增加与设置为预设图案生成的屏蔽图案间隔相对应的量来产生包括电路板中的图形元素的布线图案的屏蔽图案条件。基于要在布线图案周围进行间隙检查的元件的几何形状和用于执行间隙检查的元件与布线图案之间的间隙状态来生成禁止区域。然后，通过从基本屏蔽图案元件的几何形状排除禁止区域的几何形状来产生屏蔽图案。

25. 发明授权

US08423948B2 Wiring design support device and wiring design supporting method 有权
标题翻译：接线设计支持装置及接线设计配套方法
公开(公告)号：US08423948B2
公开(公告)日：2013-04-16
申请号：US13418470
申请日：2012-03-13
申请人： Kazunori Kumagai , Toshiyasu Sakata , Eiichi Konno
发明人： Kazunori Kumagai , Toshiyasu Sakata , Eiichi Konno
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/509
摘要： A device includes a definition unit which defines a directional graph having a grid point as a node and a line connecting adjacent grid points as a branch, a generation unit which sets a branch connecting a grid pointing a wiring prohibited area in the branches of the directional graph to the capacity of “0”, and which sets another branch to the capacity of “1”, and which connects the starting point or the end point to each grid point of the wiring terminal indicated by wiring information, thereby generating a flow network, a search unit which searches the flow network for a path of a flow having the maximum amount of flow from the starting point to the end point, and a determination unit which determines a wiring path connecting the grid point indicated by the wiring information according to the search result of the path.
摘要翻译：一种设备包括定义单元，其定义具有网格点作为节点的方向图和连接相邻网格点作为分支的线;生成单元，其设置连接指向所述方向的分支中的布线禁止区域的网格的分支图示为0的容量，并且将另一分支设置为1的容量，并且将起始点或终点连接到由布线信息指示的接线端子的每个网格点，从而生成流网络，搜索单元其在流网络中搜索具有从起始点到终点的最大流量的路径，以及确定单元，其确定根据接线信息指示的网格点的布线路径，根据搜索结果路径。

26. 发明授权

US08286124B2 Printed circuit board design assisting method, printed circuit board design assisting device, and storage medium 有权
标题翻译：印刷电路板设计辅助方法，印刷电路板设计辅助装置和存储介质
公开(公告)号：US08286124B2
公开(公告)日：2012-10-09
申请号：US12819580
申请日：2010-06-21
申请人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Kazunori Kumagai
发明人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Kazunori Kumagai
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A printed circuit board design assisting method, device and storage medium are provided. The assisting method includes referring to the position of terminals of a grid array package part, and attributes indicating whether each of the terminals is a power source terminal or a ground terminal, and selecting the power source terminals as a terminal to be researched, searching for a new connection path between the terminal which has been selected, and one of the ground terminals, by way of a first decoupling capacitor, determining whether there is duplication of paths between the new connection path and an connection path between the terminals connected by way of a second decoupling capacitor, changing the position of the second decoupling capacitor if duplication is detected, and re-searching a connection path between the terminals by way of the second decoupling capacitor, which is not in duplicate with the new connection path.
摘要翻译：提供印刷电路板设计辅助方法，装置和存储介质。辅助方法包括参考网格阵列封装部件的端子的位置以及指示每个端子是电源端子还是接地端子的属性，并且将电源端子选择为要研究的端子，搜索通过第一解耦电容器确定已经选择的终端与接地终端之一的新的连接路径，确定新连接路径和通过以下方式连接的终端之间的连接路径之间的连接路径是否重复第二去耦电容器，如果检测到复制，则改变第二去耦电容器的位置，并且通过与新连接路径不重复的第二去耦电容器重新搜索端子之间的连接路径。

27. 发明申请

US20120240094A1 WIRING DESIGN SUPPORT DEVICE AND WIRING DESIGN SUPPORTING METHOD 有权
标题翻译：接线设计支持设备和接线设计支持方法
公开(公告)号：US20120240094A1
公开(公告)日：2012-09-20
申请号：US13418470
申请日：2012-03-13
申请人： Kazunori KUMAGAI , Toshiyasu Sakata , Eiichi Konno
发明人： Kazunori KUMAGAI , Toshiyasu Sakata , Eiichi Konno
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/509
摘要： A device includes a definition unit which defines a directional graph having a grid point as a node and a line connecting adjacent grid points as a branch, a generation unit which sets a branch connecting a grid pointing a wiring prohibited area in the branches of the directional graph to the capacity of “0”, and which sets another branch to the capacity of “1”, and which connects the starting point or the end point to each grid point of the wiring terminal indicated by wiring information, thereby generating a flow network, a search unit which searches the flow network for a path of a flow having the maximum amount of flow from the starting point to the end point, and a determination unit which determines a wiring path connecting the grid point indicated by the wiring information according to the search result of the path.
摘要翻译：一种设备包括定义单元，其定义具有网格点作为节点的方向图和连接相邻网格点作为分支的线;生成单元，其设置连接指向所述方向的分支中的布线禁止区域的网格的分支以“0”的容量图表示，并将另一个分支设置为“1”的容量，并且将起始点或终点连接到由布线信息指示的接线端子的每个网格点，从而生成流网络搜索单元，其搜索流网络具有从起始点到终点的最大流量的路径，以及确定单元，确定连接由布线信息指示的网格点的布线路径，根据路径的搜索结果。

28. 发明申请

US20110231809A1 WIRING DESIGN DEVICE, METHOD AND RECORDING MEDIUM 有权
标题翻译：接线设计，方法和记录介质
公开(公告)号：US20110231809A1
公开(公告)日：2011-09-22
申请号：US13048687
申请日：2011-03-15
申请人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Kazunori Kumagai
发明人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Kazunori Kumagai
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A wiring design device to conduct wiring design on a printed wiring board that includes a plurality of conductive layers, the wiring design device including: noise contaminating part extracting means for extracting a part in a condition where noise contaminates a signal, the part being on a wiring-designed line, based on a route of the line and a physical condition around the route; route modification processing means for modifying the route of the line by moving the extracted part on the line in the condition where noise contaminates the signal to a position that avoids the condition where noise contaminates the signal; and line length adjusting means for conducting a line length adjustment on the line to compensate for a variation of the line length of the line when the variation of the line length of the line occurs due to modifying the route of the line.
摘要翻译：一种布线设计装置，用于在包括多个导电层的印刷线路板上进行布线设计，所述布线设计装置包括：噪声污染部分提取装置，用于在噪声污染信号的情况下提取部分，所述部分在基于线路的路线和路线周围的物理条件进行布线设计的线路; 路线修改处理装置，用于通过在噪声污染信号的情况下将提取的部分移动到行上来修改行的路线到避免噪声污染信号的状况的位置; 以及线长调整装置，用于当线路的线路长度的变化由于改变线路的路线而发生时，进行线路上的线路长度调整以补偿线路的线路长度的变化。

29. 发明申请

US20100325594A1 PRINTED CIRCUIT BOARD DESIGN ASSISTING METHOD, PRINTED CIRCUIT BOARD DESIGN ASSISTING DEVICE, AND STORAGE MEDIUM 有权
标题翻译：印刷电路板设计辅助方法，印刷电路板设计辅助设备和存储介质
公开(公告)号：US20100325594A1
公开(公告)日：2010-12-23
申请号：US12819580
申请日：2010-06-21
申请人： Toshiyasu SAKATA , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Kazunori Kumagai
发明人： Toshiyasu SAKATA , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Kazunori Kumagai
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A printed circuit board design assisting method, device and storage medium are provided. The assisting method includes referring to the position of terminals of a grid array package part, and attributes indicating whether each of the terminals is a power source terminal or a ground terminal, and selecting the power source terminals as a terminal to be researched, searching for a new connection path between the terminal which has been selected, and one of the ground terminals, by way of a first decoupling capacitor, determining whether there is duplication of paths between the new connection path and an connection path between the terminals connected by way of a second decoupling capacitor, changing the position of the second decoupling capacitor if duplication is detected, and re-searching a connection path between the terminals by way of the second decoupling capacitor, which is not in duplicate with the new connection path.
摘要翻译：提供印刷电路板设计辅助方法，装置和存储介质。辅助方法包括参考网格阵列封装部件的端子的位置以及指示每个端子是电源端子还是接地端子的属性，并且将电源端子选择为要研究的端子，搜索通过第一解耦电容器确定已经选择的终端与接地终端之一的新的连接路径，确定新连接路径和通过以下方式连接的终端之间的连接路径之间的连接路径是否重复第二去耦电容器，如果检测到复制，则改变第二去耦电容器的位置，并且通过与新连接路径不重复的第二去耦电容器重新搜索端子之间的连接路径。

30. 发明申请

US20100031213A1 DESIGN INFORMATION GENERATING APPARATUS 审中-公开
标题翻译：设计信息生成设备
公开(公告)号：US20100031213A1
公开(公告)日：2010-02-04
申请号：US12511549
申请日：2009-07-29
申请人： Taketsugu KAWAMICHI , Eiichi Konno
发明人： Taketsugu KAWAMICHI , Eiichi Konno
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H05K1/0269 , H05K1/0271 , H05K3/0005 , H05K2201/09918
摘要： A design information generating apparatus that generates design information of a substrate includes a substrate region generating unit that generates a plurality of substrate regions in which the substrate is arranged based on a shape of the substrate included in a design condition, when the design condition of the substrate is obtained; and a design information generating unit that generates the design information by transferring the substrate generated based on the design condition to the plurality of substrate regions after at least one of the substrate regions of the plurality of the substrate regions is inverted.
摘要翻译：产生基板的设计信息的设计信息生成装置包括基板区域生成单元，其基于设计条件中包含的基板的形状来生成基板被配置的多个基板区域，得到底物; 以及设计信息生成单元，其在多个基板区域中的至少一个基板区域反转之后，通过将基于设计条件生成的基板转印到多个基板区域来生成设计信息。

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