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21. 发明申请

US20090016103A1 MSB-BASED ERROR CORRECTION FOR FLASH MEMORY SYSTEM 有权
标题翻译：用于闪存存储器系统的基于MSB的错误校正
公开(公告)号：US20090016103A1
公开(公告)日：2009-01-15
申请号：US12169109
申请日：2008-07-08
申请人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
发明人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C2029/0411
摘要： A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.
摘要翻译：闪存系统包括具有存储单元阵列的多位闪存器件，该存储器单元阵列包括以行和列排列的存储器单元; 读取电路，被配置为从存储单元阵列读取数据; 以及控制逻辑，被配置为控制所述读取电路，以便响应于对存储在所选择的存储器单元中的MSB数据的读取操作的请求，连续地将数据从所选择的存储器单元和相邻存储器单元读取到所选择的存储器单元。比较电路被配置为将从相邻存储器单元读取的数据与从多位闪存器件提供的所选择的存储器单元进行比较，并且基于比较结果校正从所选存储器单元读取的数据。

22. 发明申请

US20080209111A1 OVER-SAMPLING READ OPERATION FOR A FLASH MEMORY DEVICE 有权
标题翻译：用于闪存存储器件的超采样读操作
公开(公告)号：US20080209111A1
公开(公告)日：2008-08-28
申请号：US12034872
申请日：2008-02-21
申请人： Dong-Ku Kang
发明人： Dong-Ku Kang
IPC分类号： G06F12/00
CPC分类号： G11C16/26 , G11C11/5642
摘要： A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation.
摘要翻译：提供闪存器件和读取方法，其中存储器单元被分成至少两组。根据阈值电压分布选择存储单元。根据第一读取操作，检测存储在所选择的存储器单元中的数据并且对应于至少两个组中的一个锁存数据。第二读取操作检测并锁存与至少两个组中的另一组对应的存储单元的数据。在第二次读取操作期间通过软判决算法处理数据。

23. 发明授权

US09373005B2 Data storage apparatus, coding unit, systems including the same, method of coding and method of reading data 有权
标题翻译：数据存储装置，编码单元，包括其的系统，编码方法和数据读取方法
公开(公告)号：US09373005B2
公开(公告)日：2016-06-21
申请号：US13445197
申请日：2012-04-12
申请人： Dong-Ku Kang
发明人： Dong-Ku Kang
IPC分类号： G06F21/71 , G06F21/74
CPC分类号： G06F12/1408 , G06F21/71 , G06F21/74 , G06F2212/1052 , G06F2212/402 , G06F2221/2105 , G06F2221/2111
摘要： In one embodiment, the data storage apparatus includes a control unit configured to decode at least one input command and configured to generate at least one of a read signal and a start signal in response to the input command. The start signal indicates to start an internal mode determination process. The data storage apparatus also includes a memory unit configured to output data in response to the read signal, and a coding unit configured to start and perform the internal mode determination process in response to the start signal. The internal mode determination process includes autonomously determining a coding mode, and the coding unit is configured to code the output data based on the determined coding mode to produce coded data.
摘要翻译：在一个实施例中，数据存储装置包括：控制单元，被配置为对至少一个输入命令进行解码，并被配置为响应于输入命令产生读取信号和起始信号中的至少一个。起始信号指示开始内部模式确定处理。数据存储装置还包括被配置为响应于读取信号而输出数据的存储单元，以及编码单元，被配置为响应于起始信号启动和执行内部模式确定处理。内部模式确定处理包括自主确定编码模式，并且编码单元被配置为基于所确定的编码模式对输出数据进行编码以产生编码数据。

24. 发明授权

US09214206B2 Method of testing non-volatile memory device and method of managing non-volatile memory device 有权
标题翻译：测试非易失性存储器件的方法和管理非易失性存储器件的方法
公开(公告)号：US09214206B2
公开(公告)日：2015-12-15
申请号：US14468736
申请日：2014-08-26
申请人： Sang-In Park , Boh-Chang Kim , Bu-il Nam , Dong-Ku Kang
发明人： Sang-In Park , Boh-Chang Kim , Bu-il Nam , Dong-Ku Kang
IPC分类号： G11C16/04 , G11C8/08 , G11C16/08 , G11C16/34 , G11C29/10 , G11C29/44 , G11C16/00 , G11C29/12
CPC分类号： G11C8/08 , G11C16/00 , G11C16/08 , G11C16/349 , G11C29/10 , G11C29/44 , G11C2029/1202
摘要： A method of testing a non-volatile memory device and a method of managing the non-volatile memory device are provided. The method of testing the non-volatile memory device includes calculating first and second values based on program loop frequencies corresponding to word lines of a memory area. A characteristic value of the memory area may be calculated based on the first and second values, and may be compared to a reference value to determine whether the memory area is defective.
摘要翻译：提供了测试非易失性存储器件的方法和管理非易失性存储器件的方法。测试非易失性存储器件的方法包括基于与存储区域的字线相对应的程序循环频率来计算第一和第二值。可以基于第一和第二值来计算存储区域的特征值，并且可以将其与参考值进行比较，以确定存储区域是否有缺陷。

25. 发明申请

US20120297150A1 DATA STORAGE APPARATUS, CODING UNIT, SYSTEMS INCLUDING THE SAME, METHOD OF CODING AND METHOD OF READING DATA 有权
标题翻译：数据存储设备，编码单元，包括其的系统，编码方法和读取数据的方法
公开(公告)号：US20120297150A1
公开(公告)日：2012-11-22
申请号：US13445197
申请日：2012-04-12
申请人： Dong-Ku Kang
发明人： Dong-Ku Kang
IPC分类号： G06F12/00
CPC分类号： G06F12/1408 , G06F21/71 , G06F21/74 , G06F2212/1052 , G06F2212/402 , G06F2221/2105 , G06F2221/2111
摘要： In one embodiment, the data storage apparatus includes a control unit configured to decode at least one input command and configured to generate at least one of a read signal and a start signal in response to the input command. The start signal indicates to start an internal mode determination process. The data storage apparatus also includes a memory unit configured to output data in response to the read signal, and a coding unit configured to start and perform the internal mode determination process in response to the start signal. The internal mode determination process includes autonomously determining a coding mode, and the coding unit is configured to code the output data based on the determined coding mode to produce coded data.
摘要翻译：在一个实施例中，数据存储装置包括：控制单元，被配置为对至少一个输入命令进行解码，并被配置为响应于输入命令产生读取信号和起始信号中的至少一个。起始信号指示开始内部模式确定处理。数据存储装置还包括被配置为响应于读取信号而输出数据的存储单元，以及编码单元，被配置为响应于起始信号启动和执行内部模式确定处理。内部模式确定处理包括自主确定编码模式，并且编码单元被配置为基于所确定的编码模式对输出数据进行编码以产生编码数据。

26. 发明授权

US08050115B2 Non-volatile memory device and method of operation therefor 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US08050115B2
公开(公告)日：2011-11-01
申请号：US12461317
申请日：2009-08-07
申请人： Dong-Ku Kang , Hee-Won Lee
发明人： Dong-Ku Kang , Hee-Won Lee
IPC分类号： G11C7/00 , G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C2211/5642
摘要： In one embodiment, the non-volatile memory device includes a plurality of normal memory cells, and at least one flag memory cell associated with one of the plurality of normal memory cells. A normal page buffer is configured to store data read from one of the plurality of normal memory cells. The normal page buffer includes a main latch storing the read data. A control circuit is configured to selectively change data stored in the main latch during a read operation based on a state of the flag memory cell.
摘要翻译：在一个实施例中，非易失性存储器件包括多个正常存储器单元，以及至少一个与多个正常存储器单元之一相关联的标志存储单元。正常页面缓冲器被配置为存储从多个正常存储器单元之一读取的数据。正常页面缓冲器包括存储读取数据的主锁存器。控制电路被配置为基于标志存储器单元的状态来选择性地改变在读取操作期间存储在主锁存器中的数据。

27. 发明授权

US08040725B2 Flash memory device and method for adjusting read voltage of flash memory device 有权
标题翻译：闪速存储器件和调整闪存器件读取电压的方法
公开(公告)号：US08040725B2
公开(公告)日：2011-10-18
申请号：US12146549
申请日：2008-06-26
申请人： Dong-Ku Kang
发明人： Dong-Ku Kang
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3454
摘要： A flash memory device includes a cell array and a read voltage adjuster. The cell array includes a first field having first memory cells and a second field having second memory cells. The read voltage adjuster determines a read voltage for reading first data from the first memory cells of the first field with reference to second data read from the memory cells of the second field.
摘要翻译：闪存器件包括单元阵列和读电压调节器。单元阵列包括具有第一存储单元的第一场和具有第二存储单元的第二场。参考从第二场的存储单元读取的第二数据，读取电压调节器确定用于从第一场的第一存储单元读取第一数据的读取电压。

28. 发明申请

US20090164710A1 SEMICONDUCTOR MEMORY SYSTEM AND ACCESS METHOD THEREOF 审中-公开
标题翻译：半导体存储器系统及其访问方法
公开(公告)号：US20090164710A1
公开(公告)日：2009-06-25
申请号：US12340846
申请日：2008-12-22
申请人： Jin-Hyeok Choi , Duck-Hyun Chang , Jun-Jin Kong , Dong-Hyuk Chae , Seung-Jae Lee , Dong-Ku Kang
发明人： Jin-Hyeok Choi , Duck-Hyun Chang , Jun-Jin Kong , Dong-Hyuk Chae , Seung-Jae Lee , Dong-Ku Kang
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G11C16/20 , G11C16/10
摘要： A semiconductor memory system and access method thereof. The semiconductor memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores monitoring data in one or more of plural memory cells. The memory controller controls the nonvolatile memory. The memory controller detects the monitoring data and adjusts a bias voltage, which is provided to the plural memory cells, in accordance with a result of the detection.
摘要翻译：半导体存储器系统及其访问方法。半导体存储器系统包括非易失性存储器和存储器控制器。非易失性存储器将监视数据存储在多个存储单元中的一个或多个中。存储器控制器控制非易失性存储器。存储器控制器根据检测结果检测监视数据并调整提供给多个存储单元的偏置电压。

29. 发明申请

US20090003058A1 FLASH MEMORY DEVICE AND METHOD FOR ADJUSTING READ VOLTAGE OF FLASH MEMORY DEVICE 有权
标题翻译：用于调整闪速存储器件的读取电压的闪速存储器件和方法
公开(公告)号：US20090003058A1
公开(公告)日：2009-01-01
申请号：US12146549
申请日：2008-06-26
申请人： Dong-Ku Kang
发明人： Dong-Ku Kang
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3454
摘要： A flash memory device includes a cell array and a read voltage adjuster. The cell array includes a first field having first memory cells and a second field having second memory cells. The read voltage adjuster determines a read voltage for reading first data from the first memory cells of the first field with reference to second data read from the memory cells of the second field.
摘要翻译：闪存器件包括单元阵列和读电压调节器。单元阵列包括具有第一存储单元的第一场和具有第二存储单元的第二场。参考从第二场的存储单元读取的第二数据，读取电压调节器确定用于从第一场的第一存储单元读取第一数据的读取电压。

30. 发明授权

US07468907B2 Programming method for flash memory capable of compensating reduction of read margin between states due to hot temperature stress 有权
标题翻译：用于闪存的编程方法能够补偿由于热温度应力导致的状态之间的读取余量的减少
公开(公告)号：US07468907B2
公开(公告)日：2008-12-23
申请号：US11522406
申请日：2006-09-18
申请人： Dong-Ku Kang , Young-Ho Lim
发明人： Dong-Ku Kang , Young-Ho Lim
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： A program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of states. The program method includes programming memory cells selected to have one of the states by using multi-bit data; detecting programmed memory cells within a predetermined region of a threshold voltage distribution where the programmed memory cells having the respective states are distributed, wherein the predetermined region of the respective states is selected by one of a first verify voltage and a read voltage and a second voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and programming the detected memory cells to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to each of the states.
摘要翻译：一种闪存器件的编程方法，包括用于存储指示状态之一的多位数据的多个存储器单元。程序方法包括通过使用多位数据来编程选择为具有状态之一的存储器单元; 在阈值电压分布的预定区域内检测已编程的存储单元，其中具有各自状态的编程存储单元被分配，其中各个状态的预定区域由第一验证电压和读取电压和第二电压第一验证电压低于第二验证电压并高于读取电压; 以及对检测到的存储单元进行编程，使阈值电压等于或高于对应于每个状态的第二验证电压。

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