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21. 发明授权

US6091707A Methods and apparatus for preventing under-flow conditions in a multiple-port switching device 失效
标题翻译：用于防止多端口开关装置中的欠流条件的方法和装置
公开(公告)号：US6091707A
公开(公告)日：2000-07-18
申请号：US993886
申请日：1997-12-18
申请人： Chandan Egbert , Bahadir Erimli , Eric Tsin-Ho Leung , Thomas J. Runaldue
发明人： Chandan Egbert , Bahadir Erimli , Eric Tsin-Ho Leung , Thomas J. Runaldue
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/54
CPC分类号： H04L49/351 , H04L49/103 , H04L49/105 , H04L49/30 , H04Q11/0478 , H04L2012/5649 , H04L2012/5651 , H04L49/20 , H04L49/3009 , H04L49/3027 , H04L49/3054 , H04L49/354
摘要： An interface for use in a data forwarding device is connected between the receive ports and transmit ports of a device. The interface ensures that data being forwarded from a receive port to a transmit port has actually been received. The interface includes a queuing circuit and a de-queuing circuit. The queuing circuit receives data from the receive port, identifies the receive port, counts the data received, and buffers the data. The de-queuing circuit retrieves the buffered data at a scheduled time based on the receive port's mode, and forwards the data to a transmit port provided that the amount of data received by the queuing circuit is at least as great as the amount of data already forwarded by the de-queuing circuit plus a threshold safe level amount of data.
摘要翻译：用于数据转发设备的接口连接在设备的接收端口和发送端口之间。该接口确保从接收端口转发到发送端口的数据已被实际接收。接口包括排队电路和排队电路。排队电路从接收端口接收数据，识别接收端口，对接收到的数据进行计数，并缓冲数据。排队电路基于接收端口的模式在预定的时间检索缓冲的数据，并且将数据转发到发送端口，只要排队电路接收的数据量至少与数据量一样大由排队电路转发加上阈值安全级别的数据量。

22. 发明授权

US6067408A Full duplex buffer management and apparatus 失效
标题翻译：全双工缓冲管理和设备
公开(公告)号：US6067408A
公开(公告)日：2000-05-23
申请号：US605532
申请日：1996-02-22
申请人： Thomas J. Runaldue , Jeffrey Roy Dwork
发明人： Thomas J. Runaldue , Jeffrey Roy Dwork
IPC分类号： G06F13/38 , H01J1/00
CPC分类号： G06F13/385
摘要： A node having a system interface adapter for intercoupling a fixed speed bus to a variable latency bus. The system interface adapter includes a receive FIFO buffer memory, a transmit FIFO buffer memory, and a memory buffer management unit. The memory buffer management unit dynamically awards priority between the two FIFOs for access to the variable latency bus in a fashion to minimize overflowing or underflowing the FIFOs while reducing the FIFO sizes. Priority between pending receive data transfers and pending transmit data transfers is resolved, in part, upon a whether a receive operation vis-a-vis the fixed-speed bus is underway.
摘要翻译：具有用于将固定速度总线互连到可变延迟总线的系统接口适配器的节点。系统接口适配器包括接收FIFO缓冲存储器，发送FIFO缓冲存储器和存储器缓冲管理单元。存储器缓冲器管理单元以两种FIFO之间的优先级动态地授予对可变延迟总线的访问，以便使FIFO溢出或下溢，同时减少FIFO大小。待处理的接收数据传输和待传输数据传输之间的优先级部分地解决了是否正在接收固定速度总线的接收操作。

23. 发明授权

US5533203A Start of packet receive interrupt for ethernet controller 失效
标题翻译：开始以太网控制器的数据包接收中断
公开(公告)号：US5533203A
公开(公告)日：1996-07-02
申请号：US437068
申请日：1995-05-09
申请人： Matthew J. Fischer , Glen Gibson , Jeffrey Dwork , Thomas J. Runaldue
发明人： Matthew J. Fischer , Glen Gibson , Jeffrey Dwork , Thomas J. Runaldue
IPC分类号： G06F13/00 , G06F13/12 , H04L12/56 , G06F15/173
CPC分类号： H04L49/9052 , G06F13/128 , H04L49/90 , H04L49/901 , H04L49/9021 , H04L49/9057 , H04L49/9073 , H04L49/9078
摘要： A system is provided for ensuring that a ethernet controller operates to optimize bus latency and central processing unit (CPU) utilization in a network environment when reviewing data packets. Through the efficient use of a plurality of buffer memories and a driver, the bus utilization in conjunction with the controller the system provides for the receipt and transfer of data packets from the ethernet controller during the latency period of the network. In so doing, the overall performance of the network is enhanced.
摘要翻译：提供了一种系统，用于确保以太网控制器在查看数据包时可以在网络环境中优化总线延迟和中央处理单元（CPU）利用率。通过有效利用多个缓冲存储器和驱动器，总线利用与控制器结合，该系统在网络的等待时间期间提供从以太网控制器接收和传送数据分组。这样做，网络的整体性能得到提升。

24. 发明授权

US5332932A Output driver circuit having reduced VSS/VDD voltage fluctuations 失效
标题翻译：输出驱动电路具有降低的VSS / VDD电压波动
公开(公告)号：US5332932A
公开(公告)日：1994-07-26
申请号：US760310
申请日：1991-09-16
申请人： Thomas J. Runaldue
发明人： Thomas J. Runaldue
IPC分类号： H03K17/16 , G11C11/409 , H03K19/003 , H03K19/0175 , H03K19/0948
CPC分类号： H03K19/00361
摘要： An output buffer driver circuit which significantly reduces the effects of voltage fluctuations in the upper and lower power supply potentials on an output signal includes a first pull-up circuit (44), a second pull-up circuit (46), a first pull-down circuit (48), a second pull-down circuit (50), a delay circuit (52), and control circuit (54). The first pull-up circuit (44) is coupled between a noisy upper power supply potential (VDDN) and output terminal (43). The second pull-up circuit (46) is coupled between a quiet upper power supply potential (VDDQ) and the output terminal. The first pull-down circuit (48) is coupled between noisy lower power supply potential (VSSN) and the output terminal. The second pull-down circuit (50) is coupled between a quiet lower power supply potential (VSSQ) and the output terminal. The second pull-up circuit (46) is delayed in its turn-on until the first pull-up circuit (44) is being turned-off when the output terminal is making the low-to-high transition so as to isolate the noisy upper power supply potential from the output terminal. Similarly, the second pull-down circuit (50) is delayed in its turn-on until the first pull-down circuit (48) is being turned-off when the output terminal is making the high-to-low transition so as to isolate the noisy lower power supply potential from the output terminal.
摘要翻译：一种输出缓冲器驱动电路，其显着降低上，下电源电压中的电压波动对输出信号的影响，包括第一上拉电路（44），第二上拉电路（46），第一上拉电路（46）下降电路（48），第二下拉电路（50），延迟电路（52）和控制电路（54）。第一上拉电路（44）耦合在噪声上电源电位（VDDN）和输出端（43）之间。第二上拉电路（46）耦合在安静的上电源电位（VDDQ）和输出端之间。第一下拉电路（48）耦合在噪声较低的电源电位（VSSN）和输出端之间。第二下拉电路（50）耦合在安静的较低电源电位（VSSQ）和输出端子之间。第二上拉电路（46）在其导通时被延迟，直到第一上拉电路（44）在输出端子进行低电平到高电平转换时截止，从而隔离噪声从输出端子上升电源电位。类似地，第二下拉电路（50）在其导通时被延迟，直到第一下拉电路（48）在输出端子进行高电平至低电平转换时截止，以便隔离输出端子的噪声较低的电源电位。

25. 发明授权

US5216636A CMOS memory cell 失效
标题翻译： CMOS MEMORY CELL
公开(公告)号：US5216636A
公开(公告)日：1993-06-01
申请号：US760655
申请日：1991-09-16
申请人： Thomas J. Runaldue
发明人： Thomas J. Runaldue
IPC分类号： G11C11/41 , G11C8/16 , H01L27/10
CPC分类号： G11C8/16
摘要： A dual port random access memory cell is coupled to complementary read/write data bit lines, a read-only data bit line, a read/write address line and a read-only address line. The memory cell includes two two-transistor inverters (36, 38) cross-coupled to form a flip-flop core memory which is coupled to complementary input/output nodes (40, 42). A fifth transistor (44 or 56) has its main electrodes connected between the first input/output node (40) and the first read/write data bit line (BLA) and its gate electrode connected to the read/write address line (ROW SELA or ROW SELA). The sixth transistor (46 or 58) has its main electrodes connected between the second input/output node (42) and the second read/write data bit line (BLA) and its gate electrode connected to the read/write address line (ROW SELA or ROW SELA). A seventh transistor (48) has its main electrodes connected between an upper power supply potential (VCC) and a common node (54) and has its gate electrode connected to the second input/output node (42). An eighth transistor (50 ) has its main electrodes connected between the common node (54) and a lower power supply potential (VSS) and its gate electrode connected to the first input/output node (40). A ninth transistor (52) has its main electrodes connected between the common node (54) and the read-only date bit line (BLB) and its gate electrode connected to the read-only address line (ROW SELB).

26. 发明授权

US5062081A Multiport memory collision/detection circuitry 失效
标题翻译：多端口内存冲突/检测电路
公开(公告)号：US5062081A
公开(公告)日：1991-10-29
申请号：US419019
申请日：1989-10-10
申请人： Thomas J. Runaldue
发明人： Thomas J. Runaldue
IPC分类号： G11C8/16
CPC分类号： G11C8/16
摘要： A multiport memory system is provided with a collision detection system to prevent collision between information which is simultaneously being read to a particular memory row and information being written to that same memory row simultaneously. Memory rows of the multiport memory system are independently addressed by address signals for a first port and by address signals corresponding to a second port. Row select signals are generated from the address signals of each of the ports when the row select signals for one particular memory row of the memory array are simultaneously present a match signal is generated. The match signal controls a forwarding logic circuit which connects the write port information directly to the read port when a match is present, providing immediate access to the most current information being written into the memory array. A write-strobe signal for entering information into the multiport memory array memory cells is provided for gating the match signal to provide a forward signal for the system.
摘要翻译：多端口存储器系统设置有冲突检测系统，以防止同时被读取到特定存储器行的信息与同时被写入同一存储器行的信息之间的冲突。多端口存储器系统的存储行由第一端口的地址信号和对应于第二端口的地址信号独立地寻址。当存储器阵列的一个特定存储器行的行选择信号同时存在匹配信号时，从每个端口的地址信号产生行选择信号。匹配信号控制转发逻辑电路，其在存在匹配时将写入端口信息直接连接到读取端口，从而立即访问被写入存储器阵列的最新信息。提供用于将信息输入到多端口存储器阵列存储器单元中的写选通信号，用于选通匹配信号以为系统提供正向信号。

27. 发明授权

US5036492A CMOS precharge and equalization circuit 失效
标题翻译： CMOS预充电和均衡电路
公开(公告)号：US5036492A
公开(公告)日：1991-07-30
申请号：US480401
申请日：1990-02-15
申请人： Thomas J. Runaldue
发明人： Thomas J. Runaldue
IPC分类号： G11C11/41 , G11C7/12 , G11C11/419
CPC分类号： G11C11/419 , G11C7/12
摘要： A CMOS precharge and equalization circuit for use with memory cells coupled between paired bit lines in a static random access memory array is constructed without the use of bleeder circuits. The precharge and equalization circuit is formed of a pair of precharge transistors and a pair of equalization transistors for precharging and equalizing the paired bit lines.

28. 发明授权

US08051160B2 Method and apparatus for a network hub to diagnose network operation and broadcast information to a remote host or monitoring device 有权
标题翻译：用于网络集线器诊断网络操作和向远程主机或监控设备广播信息的方法和装置
公开(公告)号：US08051160B2
公开(公告)日：2011-11-01
申请号：US12289194
申请日：2008-10-22
申请人： Ian Crayford , Thomas J. Runaldue
发明人： Ian Crayford , Thomas J. Runaldue
IPC分类号： G06F15/16
CPC分类号： H04L49/602 , H04L41/0213 , H04L41/022 , H04L43/0817 , H04L49/351
摘要： A network hub in a communication network that acts as a server to network clients to push, or transmit, information regarding the state of local and remote devices and networks. The information can be one, or more, status information, which information can be one or more predefined fields in a frame, which represents a packet of data. In one embodiment, it is desirable that the frame be a “legitimate” Ethernet-type frame. The status field can be a “push”-Type status field. The push operation can be a unicast, a multicast, or a broadcast, or a hybrid transmission. The hub can be a switch, repeater, a bridge, a router, a gateway, or a hybrid thereof. Also, the hub according to the present invention can be an OSI Layer 2 device, an OSI Layer 3 device, or a hybrid thereof. It is desirable that the hub be devoid of a microprocessor. As described herein, the hub may have plural ports, for example, four, eight, or more ports.
摘要翻译：通信网络中的网络集线器，充当服务器，以网络客户端推送或发送关于本地和远程设备和网络的状态的信息。该信息可以是一个或多个状态信息，哪个信息可以是表示数据分组的帧中的一个或多个预定义字段。在一个实施例中，期望该帧是“合法的”以太网类型的帧。状态字段可以是“推” - 类型状态字段。推送操作可以是单播，多播或广播或混合传输。集线器可以是交换机，中继器，网桥，路由器，网关或其混合。此外，根据本发明的集线器可以是OSI第二层设备，OSI第三层设备或其混合。希望集线器没有微处理器。如这里所述，集线器可以具有多个端口，例如四个，八个或更多个端口。

29. 发明申请

US20090063670A1 Method and apparatus for a network hub to diagnose network operation and broadcast information to a remote host or monitoring device 有权
标题翻译：用于网络集线器诊断网络操作和向远程主机或监控设备广播信息的方法和装置
公开(公告)号：US20090063670A1
公开(公告)日：2009-03-05
申请号：US12289194
申请日：2008-10-22
申请人： Ian Crayford , Thomas J. Runaldue
发明人： Ian Crayford , Thomas J. Runaldue
IPC分类号： G06F15/16
CPC分类号： H04L49/602 , H04L41/0213 , H04L41/022 , H04L43/0817 , H04L49/351
摘要： A network hub in a communication network that acts as a server to network clients to push, or transmit, information regarding the state of local and remote devices and networks. The information can be one, or more, status information, which information can be one or more predefined fields in a frame, which represents a packet of data. In one embodiment, it is desirable that the frame be a “legitimate” Ethernet-type frame. The status field can be a “push”-Type status field. The push operation can be a unicast, a multicast, or a broadcast, or a hybrid transmission. The hub can be a switch, repeater, a bridge, a router, a gateway, or a hybrid thereof. Also, the hub according to the present invention can be an OSI Layer 2 device, an OSI Layer 3 device, or a hybrid thereof. It is desirable that the hub be devoid of a microprocessor. As described herein, the hub may have plural ports, for example, four, eight, or more ports.
摘要翻译：通信网络中的网络集线器，充当服务器，以网络客户端推送或发送关于本地和远程设备和网络的状态的信息。该信息可以是一个或多个状态信息，哪个信息可以是表示数据分组的帧中的一个或多个预定义字段。在一个实施例中，期望该帧是“合法的”以太网类型的帧。状态字段可以是“推” - 类型状态字段。推送操作可以是单播，多播或广播或混合传输。集线器可以是交换机，中继器，网桥，路由器，网关或其混合。此外，根据本发明的集线器可以是OSI第二层设备，OSI第三层设备或其混合。希望集线器没有微处理器。如这里所述，集线器可以具有多个端口，例如四个，八个或更多个端口。

30. 发明授权

US07457857B1 Method and apparatus for a network hub to diagnose network operation and broadcast information to a remote host or monitoring device 有权
标题翻译：用于网络集线器诊断网络操作和向远程主机或监控设备广播信息的方法和装置
公开(公告)号：US07457857B1
公开(公告)日：2008-11-25
申请号：US09580665
申请日：2000-05-26
申请人： Ian Crayford , Thomas J. Runaldue
发明人： Ian Crayford , Thomas J. Runaldue
IPC分类号： G06F15/16
CPC分类号： H04L49/602 , H04L41/0213 , H04L41/022 , H04L43/0817 , H04L49/351
摘要： A network hub in a communication network that acts as a server to network clients to push, or transmit, information regarding the state of local and remote devices and networks. The information can be one, or more, status information, which information can be one or more predefined fields in a frame, which represents a packet of data. In one embodiment, it is desirable that the frame be a “legitimate” Ethernet-type frame. The status field can be a “push”-Type status field. The push operation can be a unicast, a multicast, or a broadcast, or a hybrid transmission. The hub can be a switch, repeater, a bridge, a router, a gateway, or a hybrid thereof. Also, the hub according to the present invention can be an OSI Layer 2 device, an OSI Layer 3 device, or a hybrid thereof. It is desirable that the hub be devoid of a microprocessor. As described herein, the hub may have plural ports, for example, four, eight, or more ports.
摘要翻译：通信网络中的网络集线器，充当服务器，以网络客户端推送或发送关于本地和远程设备和网络的状态的信息。该信息可以是一个或多个状态信息，哪个信息可以是表示数据分组的帧中的一个或多个预定义字段。在一个实施例中，期望该帧是“合法的”以太网类型的帧。状态字段可以是“推” - 类型状态字段。推送操作可以是单播，多播或广播或混合传输。集线器可以是交换机，中继器，网桥，路由器，网关或其混合。此外，根据本发明的集线器可以是OSI第二层设备，OSI第三层设备或其混合。希望集线器没有微处理器。如这里所述，集线器可以具有多个端口，例如四个，八个或更多个端口。

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