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21. 发明授权

US5576560A Dual port memory, such as used in color lookup tables for video systems 失效
标题翻译：双端口存储器，例如用于视频系统的颜色查找表
公开(公告)号：US5576560A
公开(公告)日：1996-11-19
申请号：US267036
申请日：1994-06-27
申请人： Thomas J. Runaldue , William Plants
发明人： Thomas J. Runaldue , William Plants
IPC分类号： G09G5/00 , G06T1/20 , G06T1/60 , G09G5/06 , G11C7/10 , H01L21/8244 , H01L27/11 , H01L27/10
CPC分类号： H01L27/1104 , G09G5/06 , G11C7/1075 , Y10S257/903
摘要： An integrated circuit memory for a color lookup table for a display system. The memory has a video port and path for reading data identifying colors for pixels at >100 or even >200 MegaHertz, and a CPU port and path for reading and writing data identifying colors at locations in the memory.Each memory cell includes a flip-flop with true and complement terminals. The CPU port includes two pass transistors, each having a first channel terminal coupled to the true or complement terminal, a second channel terminal coupled to a bidirectional bit line of the CPU path, and a gate coupled to a word line of the CPU path. The video port includes an isolated sensing terminal and two transistors. A first transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a reference, and a gate coupled to the true or complement terminal. A second transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a bit line of the video path, and a gate coupled to a word line of the video path.A layout configuration of each memory cell and of the memory cell array allows same-channel-type transistors from a plurality of memory cells to be formed in a single, large well, and allows adjacent memory cells to share contacts. This reduces the integrated circuit's size, improves its speed, and increases manufacturing yields.
摘要翻译：一种用于显示系统的颜色查找表的集成电路存储器。存储器具有视频端口和路径，用于读取识别> 100或甚至> 200兆比特的像素的颜色的数据，以及用于读取和写入识别存储器中的位置处的颜色的数据的CPU端口和路径。每个存储单元包括具有真和补码端子的触发器。 CPU端口包括两个通过晶体管，每个具有耦合到真实或补充端子的第一通道端子，耦合到CPU路径的双向位线的第二通道端子以及耦合到CPU路径的字线的栅极。视频端口包括隔离的感测端子和两个晶体管。第一晶体管具有耦合到隔离感测端子的第一通道端子，耦合到参考电压的第二通道端子和耦合到真或补体端子的栅极。第二晶体管具有耦合到隔离感测端子的第一通道端子，耦合到视频通路的位线的第二通道端子和耦合到视频通路的字线的栅极。每个存储单元和存储单元阵列的布局配置允许在单个大的阱中形成来自多个存储单元的相同通道型晶体管，并允许相邻的存储单元共享触点。这降低了集成电路的尺寸，提高了其速度，并提高了制造成品率。

22. 发明授权

US5325338A Dual port memory, such as used in color lookup tables for video systems 失效
标题翻译：双端口存储器，例如用于视频系统的颜色查找表
公开(公告)号：US5325338A
公开(公告)日：1994-06-28
申请号：US754910
申请日：1991-09-04
申请人： Thomas J. Runaldue , William Plants
发明人： Thomas J. Runaldue , William Plants
IPC分类号： G09G5/00 , G06T1/20 , G06T1/60 , G09G5/06 , G11C7/10 , H01L21/8244 , H01L27/11 , G11C7/00 , G09G1/28
CPC分类号： H01L27/1104 , G09G5/06 , G11C7/1075 , Y10S257/903
摘要： An integrated circuit memory for a color lookup table for a display system. The memory has a video port and path for reading data identifying colors for pixels at >100 or even >200 MegaHertz, and a CPU port and path for reading and writing data identifying colors at locations in the memory. Each memory cell includes a flip-flop with true and complement terminals. The CPU port includes two pass transistors, each having a first channel terminal coupled to the true or complement terminal, a second channel terminal coupled to a bidirectional bit line of the CPU path, and a gate coupled to a word line of the CPU path. The video port includes an isolated sensing terminal and two transistors. A first transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a reference, and a gate coupled to the true or complement terminal. A second transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a bit line of the video path, and a gate coupled to a word line of the video path.
摘要翻译：一种用于显示系统的颜色查找表的集成电路存储器。存储器具有视频端口和路径，用于读取识别> 100或甚至> 200兆比特的像素的颜色的数据，以及用于读取和写入识别存储器中的位置处的颜色的数据的CPU端口和路径。每个存储单元包括具有真和补码端子的触发器。 CPU端口包括两个通过晶体管，每个具有耦合到真实或补充端子的第一通道端子，耦合到CPU路径的双向位线的第二通道端子以及耦合到CPU路径的字线的栅极。视频端口包括隔离的感测端子和两个晶体管。第一晶体管具有耦合到隔离感测端子的第一通道端子，耦合到参考电压的第二通道端子和耦合到真或补体端子的栅极。第二晶体管具有耦合到隔离感测端子的第一通道端子，耦合到视频通路的位线的第二通道端子和耦合到视频通路的字线的栅极。

23. 发明授权

US5067110A Global reset and zero detection for a memory system 失效
标题翻译：一个内存系统的全局复位和零检测
公开(公告)号：US5067110A
公开(公告)日：1991-11-19
申请号：US418680
申请日：1989-10-10
申请人： Thomas J. Runaldue
发明人： Thomas J. Runaldue
IPC分类号： G11C7/20
CPC分类号： G11C7/20
摘要： A tag bit is provided for each row of a memory array. The tag bit is zero is all of the bits in a row are zeros. A detector scans input data to test for all zeros and the tag bit is reset to zero. The output signals for a row are forced to zero when the tag bit for that row is zero.
摘要翻译：为存储器阵列的每一行提供标记位。标签位为零，所有位都是零。检测器扫描输入数据以测试全零，标记位复位为零。当该行的标签位为零时，一行的输出信号被强制为零。

24. 发明授权

US6160436A Driver with switchable gain 有权
标题翻译：驱动器具有可切换增益
公开(公告)号：US6160436A
公开(公告)日：2000-12-12
申请号：US281905
申请日：1999-03-31
申请人： Thomas J. Runaldue
发明人： Thomas J. Runaldue
IPC分类号： H04J3/06 , H04L12/24 , H04L12/413 , H04L25/02 , H04L25/03 , H04L29/06 , H04L29/08 , H03K17/62
CPC分类号： H04L25/03885 , H04J3/0688 , H04L12/40032 , H04L12/413 , H04L25/0266 , H04L25/0272 , H04L41/046 , H04L49/3054 , H04L69/323
摘要： A driver having a switchable gain including a first circuit connected to a potential source, an input node receiving an input current, and an output node and operable in both low and high transmission frequency modes, and a second circuit connected to the potential source and a node of the first circuit and operable in only the high transmission frequency mode. In the low transmission frequency mode, the potential source is at a first level and the first circuit receives the input current and provides a first output current with a first current gain to the output node. In the high transmission frequency mode, the potential source is at a second, lower level and the first and second circuits receive the input current and provide a second output current, less than the first output current, with a second current gain, lower than the first current gain, to the output node.
摘要翻译：具有可切换增益的驱动器，包括连接到电位源的第一电路，接收输入电流的输入节点和可在低和高传输频率模式中工作的输出节点，以及连接到潜在源的第二电路和节点，并且仅在高传输频率模式下操作。在低透射频率模式中，电位源处于第一电平，第一电路接收输入电流，并向输出节点提供具有第一电流增益的第一输出电流。在高传输频率模式中，电位源处于第二低电平，第一和第二电路接收输入电流，并提供小于第一输出电流的第二输出电流，第二电流增益低于第一个当前增益，输出节点。

25. 发明授权

US6067408A Full duplex buffer management and apparatus 失效
标题翻译：全双工缓冲管理和设备
公开(公告)号：US6067408A
公开(公告)日：2000-05-23
申请号：US605532
申请日：1996-02-22
申请人： Thomas J. Runaldue , Jeffrey Roy Dwork
发明人： Thomas J. Runaldue , Jeffrey Roy Dwork
IPC分类号： G06F13/38 , H01J1/00
CPC分类号： G06F13/385
摘要： A node having a system interface adapter for intercoupling a fixed speed bus to a variable latency bus. The system interface adapter includes a receive FIFO buffer memory, a transmit FIFO buffer memory, and a memory buffer management unit. The memory buffer management unit dynamically awards priority between the two FIFOs for access to the variable latency bus in a fashion to minimize overflowing or underflowing the FIFOs while reducing the FIFO sizes. Priority between pending receive data transfers and pending transmit data transfers is resolved, in part, upon a whether a receive operation vis-a-vis the fixed-speed bus is underway.
摘要翻译：具有用于将固定速度总线互连到可变延迟总线的系统接口适配器的节点。系统接口适配器包括接收FIFO缓冲存储器，发送FIFO缓冲存储器和存储器缓冲管理单元。存储器缓冲器管理单元以两种FIFO之间的优先级动态地授予对可变延迟总线的访问，以便使FIFO溢出或下溢，同时减少FIFO大小。待处理的接收数据传输和待传输数据传输之间的优先级部分地解决了是否正在接收固定速度总线的接收操作。

26. 发明授权

US5533203A Start of packet receive interrupt for ethernet controller 失效
标题翻译：开始以太网控制器的数据包接收中断
公开(公告)号：US5533203A
公开(公告)日：1996-07-02
申请号：US437068
申请日：1995-05-09
申请人： Matthew J. Fischer , Glen Gibson , Jeffrey Dwork , Thomas J. Runaldue
发明人： Matthew J. Fischer , Glen Gibson , Jeffrey Dwork , Thomas J. Runaldue
IPC分类号： G06F13/00 , G06F13/12 , H04L12/56 , G06F15/173
CPC分类号： H04L49/9052 , G06F13/128 , H04L49/90 , H04L49/901 , H04L49/9021 , H04L49/9057 , H04L49/9073 , H04L49/9078
摘要： A system is provided for ensuring that a ethernet controller operates to optimize bus latency and central processing unit (CPU) utilization in a network environment when reviewing data packets. Through the efficient use of a plurality of buffer memories and a driver, the bus utilization in conjunction with the controller the system provides for the receipt and transfer of data packets from the ethernet controller during the latency period of the network. In so doing, the overall performance of the network is enhanced.
摘要翻译：提供了一种系统，用于确保以太网控制器在查看数据包时可以在网络环境中优化总线延迟和中央处理单元（CPU）利用率。通过有效利用多个缓冲存储器和驱动器，总线利用与控制器结合，该系统在网络的等待时间期间提供从以太网控制器接收和传送数据分组。这样做，网络的整体性能得到提升。

27. 发明授权

US5332932A Output driver circuit having reduced VSS/VDD voltage fluctuations 失效
标题翻译：输出驱动电路具有降低的VSS / VDD电压波动
公开(公告)号：US5332932A
公开(公告)日：1994-07-26
申请号：US760310
申请日：1991-09-16
申请人： Thomas J. Runaldue
发明人： Thomas J. Runaldue
IPC分类号： H03K17/16 , G11C11/409 , H03K19/003 , H03K19/0175 , H03K19/0948
CPC分类号： H03K19/00361
摘要： An output buffer driver circuit which significantly reduces the effects of voltage fluctuations in the upper and lower power supply potentials on an output signal includes a first pull-up circuit (44), a second pull-up circuit (46), a first pull-down circuit (48), a second pull-down circuit (50), a delay circuit (52), and control circuit (54). The first pull-up circuit (44) is coupled between a noisy upper power supply potential (VDDN) and output terminal (43). The second pull-up circuit (46) is coupled between a quiet upper power supply potential (VDDQ) and the output terminal. The first pull-down circuit (48) is coupled between noisy lower power supply potential (VSSN) and the output terminal. The second pull-down circuit (50) is coupled between a quiet lower power supply potential (VSSQ) and the output terminal. The second pull-up circuit (46) is delayed in its turn-on until the first pull-up circuit (44) is being turned-off when the output terminal is making the low-to-high transition so as to isolate the noisy upper power supply potential from the output terminal. Similarly, the second pull-down circuit (50) is delayed in its turn-on until the first pull-down circuit (48) is being turned-off when the output terminal is making the high-to-low transition so as to isolate the noisy lower power supply potential from the output terminal.
摘要翻译：一种输出缓冲器驱动电路，其显着降低上，下电源电压中的电压波动对输出信号的影响，包括第一上拉电路（44），第二上拉电路（46），第一上拉电路（46）下降电路（48），第二下拉电路（50），延迟电路（52）和控制电路（54）。第一上拉电路（44）耦合在噪声上电源电位（VDDN）和输出端（43）之间。第二上拉电路（46）耦合在安静的上电源电位（VDDQ）和输出端之间。第一下拉电路（48）耦合在噪声较低的电源电位（VSSN）和输出端之间。第二下拉电路（50）耦合在安静的较低电源电位（VSSQ）和输出端子之间。第二上拉电路（46）在其导通时被延迟，直到第一上拉电路（44）在输出端子进行低电平到高电平转换时截止，从而隔离噪声从输出端子上升电源电位。类似地，第二下拉电路（50）在其导通时被延迟，直到第一下拉电路（48）在输出端子进行高电平至低电平转换时截止，以便隔离输出端子的噪声较低的电源电位。

28. 发明授权

US5216636A CMOS memory cell 失效
标题翻译： CMOS MEMORY CELL
公开(公告)号：US5216636A
公开(公告)日：1993-06-01
申请号：US760655
申请日：1991-09-16
申请人： Thomas J. Runaldue
发明人： Thomas J. Runaldue
IPC分类号： G11C11/41 , G11C8/16 , H01L27/10
CPC分类号： G11C8/16
摘要： A dual port random access memory cell is coupled to complementary read/write data bit lines, a read-only data bit line, a read/write address line and a read-only address line. The memory cell includes two two-transistor inverters (36, 38) cross-coupled to form a flip-flop core memory which is coupled to complementary input/output nodes (40, 42). A fifth transistor (44 or 56) has its main electrodes connected between the first input/output node (40) and the first read/write data bit line (BLA) and its gate electrode connected to the read/write address line (ROW SELA or ROW SELA). The sixth transistor (46 or 58) has its main electrodes connected between the second input/output node (42) and the second read/write data bit line (BLA) and its gate electrode connected to the read/write address line (ROW SELA or ROW SELA). A seventh transistor (48) has its main electrodes connected between an upper power supply potential (VCC) and a common node (54) and has its gate electrode connected to the second input/output node (42). An eighth transistor (50 ) has its main electrodes connected between the common node (54) and a lower power supply potential (VSS) and its gate electrode connected to the first input/output node (40). A ninth transistor (52) has its main electrodes connected between the common node (54) and the read-only date bit line (BLB) and its gate electrode connected to the read-only address line (ROW SELB).

29. 发明授权

US5062081A Multiport memory collision/detection circuitry 失效
标题翻译：多端口内存冲突/检测电路
公开(公告)号：US5062081A
公开(公告)日：1991-10-29
申请号：US419019
申请日：1989-10-10
申请人： Thomas J. Runaldue
发明人： Thomas J. Runaldue
IPC分类号： G11C8/16
CPC分类号： G11C8/16
摘要： A multiport memory system is provided with a collision detection system to prevent collision between information which is simultaneously being read to a particular memory row and information being written to that same memory row simultaneously. Memory rows of the multiport memory system are independently addressed by address signals for a first port and by address signals corresponding to a second port. Row select signals are generated from the address signals of each of the ports when the row select signals for one particular memory row of the memory array are simultaneously present a match signal is generated. The match signal controls a forwarding logic circuit which connects the write port information directly to the read port when a match is present, providing immediate access to the most current information being written into the memory array. A write-strobe signal for entering information into the multiport memory array memory cells is provided for gating the match signal to provide a forward signal for the system.
摘要翻译：多端口存储器系统设置有冲突检测系统，以防止同时被读取到特定存储器行的信息与同时被写入同一存储器行的信息之间的冲突。多端口存储器系统的存储行由第一端口的地址信号和对应于第二端口的地址信号独立地寻址。当存储器阵列的一个特定存储器行的行选择信号同时存在匹配信号时，从每个端口的地址信号产生行选择信号。匹配信号控制转发逻辑电路，其在存在匹配时将写入端口信息直接连接到读取端口，从而立即访问被写入存储器阵列的最新信息。提供用于将信息输入到多端口存储器阵列存储器单元中的写选通信号，用于选通匹配信号以为系统提供正向信号。

30. 发明授权

US5036492A CMOS precharge and equalization circuit 失效
标题翻译： CMOS预充电和均衡电路
公开(公告)号：US5036492A
公开(公告)日：1991-07-30
申请号：US480401
申请日：1990-02-15
申请人： Thomas J. Runaldue
发明人： Thomas J. Runaldue
IPC分类号： G11C11/41 , G11C7/12 , G11C11/419
CPC分类号： G11C11/419 , G11C7/12
摘要： A CMOS precharge and equalization circuit for use with memory cells coupled between paired bit lines in a static random access memory array is constructed without the use of bleeder circuits. The precharge and equalization circuit is formed of a pair of precharge transistors and a pair of equalization transistors for precharging and equalizing the paired bit lines.

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