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21. 发明申请

US20120007054A1 Self-Aligned Contacts in Carbon Devices 有权
标题翻译：碳装置中的自对准触点
公开(公告)号：US20120007054A1
公开(公告)日：2012-01-12
申请号：US12832224
申请日：2010-07-08
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/76 , H01L29/78 , H01L27/12 , H01L29/24 , H01L21/86 , H01L21/04
CPC分类号： H01L29/1606 , B82Y10/00 , H01L29/165 , H01L29/41733 , H01L29/41766 , H01L29/41775 , H01L29/66431 , H01L29/66742 , H01L29/7781 , H01L29/78 , H01L29/78684 , H01L51/0048
摘要： A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity.
摘要翻译：一种用于形成半导体器件的方法包括在基片上形成碳材料，在碳材料上形成栅叠层，去除基片的一部分以形成由碳材料和基片的一部分限定的至少一个空腔，以及在所述至少一个空腔中形成导电接触。

22. 发明申请

US20110248362A1 SELF-ALIGNED CONTACTS 有权
标题翻译：自对准联系人
公开(公告)号：US20110248362A1
公开(公告)日：2011-10-13
申请号：US12755752
申请日：2010-04-07
申请人： Dechao Guo , Wilfried E.A. Haensch , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Wilfried E.A. Haensch , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/28008 , H01L21/28052 , H01L21/28097 , H01L21/76897 , H01L29/517 , H01L29/66507 , H01L29/66545
摘要： A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.
摘要翻译：提供了一种形成具有自对准接触的栅极结构的方法，并且包括将牺牲层和次级层顺序地沉积到设置在栅极结构的位置处的多晶硅上，封装牺牲层，第二层和聚 -Si，通过形成在次级层中的开口去除牺牲层，并在至少由牺牲层正式占据的空间内形成硅化物。

23. 发明申请

US20110215300A1 GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE 有权
标题翻译：基于GRAPHENE的三维集成电路设备
公开(公告)号：US20110215300A1
公开(公告)日：2011-09-08
申请号：US12719058
申请日：2010-03-08
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
IPC分类号： H01L27/088 , H01L21/8256
CPC分类号： H01L27/0688 , H01L29/1606 , Y10S977/755
摘要： A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.
摘要翻译：三维（3D）集成电路（IC）结构包括在衬底上形成的第一层石墨烯; 使用第一层石墨烯形成的一个或多个有源器件的第一级; 绝缘层，形成在一个或多个有源器件的第一级上; 在所述绝缘层上形成的第二层石墨烯; 以及使用第二层石墨烯形成的一个或多个有源器件的第二电平，一个或多个有源器件的第二电平与一个或多个有源器件的第一电平电互连。

24. 发明授权

US09041057B2 Field effect transistor device with shaped conduction channel 有权
标题翻译：具有形状导通通道的场效应晶体管器件
公开(公告)号：US09041057B2
公开(公告)日：2015-05-26
申请号：US13551164
申请日：2012-07-17
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/78 , H01L29/10 , H01L29/165 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78 , H01L29/1037 , H01L29/1054 , H01L29/165 , H01L29/4236 , H01L29/66621
摘要： A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.
摘要翻译：场效应晶体管器件包括衬底，设置在衬底上的硅锗（SiGe）层，衬在由衬底和硅锗层限定的空腔的表面上的栅介质层，栅极介电层上的金属栅极材料，填充空腔的金属栅极材料，源极区域和漏极区域。

25. 发明授权

US08309418B2 Field effect transistor device with shaped conduction channel 有权
标题翻译：具有形状导通通道的场效应晶体管器件
公开(公告)号：US08309418B2
公开(公告)日：2012-11-13
申请号：US12860977
申请日：2010-08-23
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L29/1037 , H01L29/1054 , H01L29/165 , H01L29/4236 , H01L29/66621
摘要： A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.
摘要翻译：场效应晶体管器件包括衬底，设置在衬底上的硅锗（SiGe）层，衬在由衬底和硅锗层限定的空腔的表面上的栅介质层，栅极介电层上的金属栅极材料，填充空腔的金属栅极材料，源极区域和漏极区域。

26. 发明授权

US08946853B2 Diffusion sidewall for a semiconductor structure 有权
标题翻译：半导体结构的扩散侧壁
公开(公告)号：US08946853B2
公开(公告)日：2015-02-03
申请号：US13351041
申请日：2012-01-16
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
IPC分类号： H01L29/06 , H01L21/762 , H01L21/84 , H01L27/12
CPC分类号： H01L21/76224 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.
摘要翻译：在半导体结构中形成扩散侧壁的方法和具有扩散侧壁的半导体结构的方法包括将沟槽蚀刻到半导体衬底中以形成第一和第二有源区，沿着有源硅区（RX ）去除沿着第一和第二有源区域之一的RX区域的暴露的侧壁形成的氧化物衬垫，通过在RX的暴露侧壁内外延生长原位掺杂材料来形成扩散侧壁区域，并且在第一和第二有源区域之间的沟槽内形成隔离区域，以将第一和第二有源区域彼此电隔离。

27. 发明授权

US08536651B2 Multi-gate transistor having sidewall contacts 有权
标题翻译：具有侧壁接触的多栅极晶体管
公开(公告)号：US08536651B2
公开(公告)日：2013-09-17
申请号：US13604340
申请日：2012-09-05
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/785 , H01L29/66795 , H01L2029/7858
摘要： A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.
摘要翻译：一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。

28. 发明授权

US08138547B2 MOSFET on silicon-on-insulator REDX with asymmetric source-drain contacts 有权
标题翻译： MOSFET上绝缘体上的REDX具有不对称的源极 - 漏极触点
公开(公告)号：US08138547B2
公开(公告)日：2012-03-20
申请号：US12548005
申请日：2009-08-26
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/84 , H01L29/41733 , H01L29/458 , H01L29/66772 , H01L29/7839 , H01L29/78624
摘要： A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region.
摘要翻译：公开了一种半导体器件，其包括绝缘体上硅衬底，其包括掩埋绝缘体层和上覆半导体层。在半导体层中形成源延伸和漏扩展区。在半导体层中形成深漏极区域和深源极区域。第一金属 - 半导体合金接触层使用倾斜的金属形成，以朝向源延伸区域倾斜的角度形成，使得源极延伸区域具有金属 - 半导体合金接触件，其从源极侧邻接衬底，作为肖特基接触并且栅极屏蔽金属沉积物抵靠深漏极区域。在源极延伸区域和漏极延伸区域中的每一个上，在第一金属 - 半导体层上形成第二金属 - 半导体合金接触。

29. 发明申请

US20120043585A1 Field Effect Transistor Device with Shaped Conduction Channel 有权
公开(公告)号：US20120043585A1
公开(公告)日：2012-02-23
申请号：US12860977
申请日：2010-08-23
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/78 , H01L21/335 , H01L29/772
CPC分类号： H01L29/78 , H01L29/1037 , H01L29/1054 , H01L29/165 , H01L29/4236 , H01L29/66621
摘要： A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.

30. 发明申请

US20120007183A1 Multi-gate Transistor Having Sidewall Contacts 有权
标题翻译：具有侧壁触点的多栅极晶体管
公开(公告)号：US20120007183A1
公开(公告)日：2012-01-12
申请号：US12832829
申请日：2010-07-08
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/785 , H01L29/66795 , H01L2029/7858
摘要： A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.
摘要翻译：一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。

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