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21. 发明授权

US06419844B1 Method for fabricating calibration target for calibrating semiconductor wafer test systems 失效
标题翻译：制造用于校准半导体晶片测试系统的校准目标的方法
公开(公告)号：US06419844B1
公开(公告)日：2002-07-16
申请号：US09469339
申请日：1999-12-20
申请人： Andrew J. Krivy , Warren M. Farnworth , David R. Hembree , Salman Akram , James M. Wark , John O. Jacobson
发明人： Andrew J. Krivy , Warren M. Farnworth , David R. Hembree , Salman Akram , James M. Wark , John O. Jacobson
IPC分类号： H01L2100
CPC分类号： G01R35/005 , G01R1/073 , Y10T29/49197
摘要： A calibration target for calibrating semiconductor wafer test systems including probe testers and probe card analyzers is provided. Also provided are calibration methods using the calibration target, and a method for fabricating the calibration target. The calibration target includes a substrate with various three dimensional alignment features formed thereon. A first type of alignment feature includes a contrast layer and an alignment fiducial formed on a tip portion thereof. The contrast layer and alignment fiducial are configured for viewing by a viewing device of the probe card analyzer, or the test system, to achieve X-direction and Y-direction calibration. A second type of alignment feature includes a conductive layer formed on a tip portion thereof, which is configured to electrically engage a contact on a check plate of the probe card analyzer, or a probe contact on a probe card of the test system, to achieve Z-direction calibration. The alignment features can be formed by forming raised members on a silicon substrate, and depositing and etching metal layers on the raised members.
摘要翻译：提供了用于校准包括探针测试仪和探针卡分析仪在内的半导体晶片测试系统的校准目标。还提供了使用校准目标的校准方法以及用于制造校准目标的方法。校准目标包括其上形成有各种三维对准特征的基板。第一类型的对准特征包括形成在其顶端部分上的对比层和对准基准。对比层和对准基准被配置为通过探针卡分析仪或测试系统的观察装置进行观察，以实现X方向和Y方向校准。第二类型的对准特征包括形成在其尖端部分上的导电层，其被配置为与探针卡分析器的支撑板上的触点或测试系统的探针卡上的探针接触电接合，以实现 Z向校准。对准特征可以通过在硅衬底上形成凸起构件，以及在凸起构件上沉积和蚀刻金属层来形成。

22. 发明授权

US06208157B1 Method for testing semiconductor components 有权
标题翻译：半导体元件测试方法
公开(公告)号：US06208157B1
公开(公告)日：2001-03-27
申请号：US09298769
申请日：1999-04-23
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
IPC分类号： G01R3102
CPC分类号： G01R1/0466 , G01R1/0433 , G01R1/0483
摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.
摘要翻译：提供了一种用于测试半导体部件的系统和方法。该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装在插座上用于容纳组件的载体。载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

23. 发明授权

US5955877A Method and apparatus for automatically positioning electronic dice within component packages 有权
标题翻译：电子管芯在组件封装内自动定位的方法和装置
公开(公告)号：US5955877A
公开(公告)日：1999-09-21
申请号：US170844
申请日：1998-10-13
申请人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
发明人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
IPC分类号： G01R31/26 , G01R31/28 , G01R31/311 , H01L21/00 , H01L21/60 , H01L21/66 , H01L21/68 , H05K13/08
CPC分类号： H01L21/67276 , G01R31/2851 , G01R31/2886 , G01R31/2893 , H01L21/67126 , H01L21/67242 , H01L21/67259 , H01L21/681 , H01L24/74 , H05K13/08 , G01R31/311 , H01L2924/12042 , H01L2924/14 , Y10T29/49004 , Y10T29/49131 , Y10T29/53174 , Y10T29/53178
摘要： A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).
摘要翻译：从临时测试包的组件组装和拆卸要测试的半导体骰子的方法和装置。采用计算机控制的视觉系统将骰子与临时测试包基座对准，并且采用自动机器人手臂系统来检索和组装骰子与各种包装部件。本发明在骰子的老化和其他预包装测试中具有特殊的用途，以建立已知的骰子（KGD）。

24. 发明授权

US06210984B1 Method and apparatus for automatically positioning electronic dice within component packages 有权
标题翻译：电子管芯在组件封装内自动定位的方法和装置
公开(公告)号：US06210984B1
公开(公告)日：2001-04-03
申请号：US09399640
申请日：1999-09-20
申请人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
发明人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
IPC分类号： H01L2166
CPC分类号： H01L21/67276 , G01R31/2851 , G01R31/2886 , G01R31/2893 , G01R31/311 , H01L21/67126 , H01L21/67242 , H01L21/67259 , H01L21/681 , H01L24/74 , H01L2924/12042 , H01L2924/14 , H05K13/08 , Y10T29/49004 , Y10T29/49131 , Y10T29/53174 , Y10T29/53178 , H01L2924/00
摘要： A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).
摘要翻译：从临时测试包的组件组装和拆卸要测试的半导体骰子的方法和装置。采用计算机控制的视觉系统将骰子与临时测试包基座对准，并且采用自动机器人手臂系统来检索和组装骰子与各种包装部件。本发明在骰子的老化和其他预包装测试中具有特殊的用途，以建立已知的骰子（KGD）。

25. 发明授权

US06396291B1 Method for testing semiconductor components 失效
标题翻译：半导体元件测试方法
公开(公告)号：US06396291B1
公开(公告)日：2002-05-28
申请号：US09723101
申请日：2000-11-28
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
IPC分类号： G01R3102
CPC分类号： G01R1/0466 , G01R1/0483
摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.
摘要翻译：提供了一种用于测试半导体部件的系统和方法。该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装到插座以用于容纳部件的载体。载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

26. 发明授权

US6072326A System for testing semiconductor components 失效
标题翻译：半导体元件测试系统
公开(公告)号：US6072326A
公开(公告)日：2000-06-06
申请号：US916434
申请日：1997-08-22
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
IPC分类号： G01R1/04 , G01R31/02
CPC分类号： G01R1/0466 , G01R1/0433 , G01R1/0483
摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.
摘要翻译：提供了一种用于测试半导体部件的系统和方法。该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装到插座以用于容纳部件的载体。载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

27. 发明授权

US06998334B2 Semiconductor devices with permanent polymer stencil and method for manufacturing the same 有权
公开(公告)号：US06998334B2
公开(公告)日：2006-02-14
申请号：US10191424
申请日：2002-07-08
申请人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Syed Sajid Ahmad , Michael E. Hess , John O. Jacobson
发明人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Syed Sajid Ahmad , Michael E. Hess , John O. Jacobson
IPC分类号： H01L21/44
CPC分类号： H01L23/544 , B33Y30/00 , B33Y80/00 , H01L21/563 , H01L23/293 , H01L23/3157 , H01L24/81 , H01L24/83 , H01L2223/5448 , H01L2224/05571 , H01L2224/05573 , H01L2224/11005 , H01L2224/1147 , H01L2224/11472 , H01L2224/16 , H01L2224/293 , H01L2224/81011 , H01L2224/8121 , H01L2224/81815 , H01L2224/83851 , H01L2924/00014 , H01L2924/01078 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/3512 , H01L2924/00 , H01L2224/05599
摘要： Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces of the semiconductor devices.

28. 发明授权

US06900459B2 Apparatus for automatically positioning electronic dice within component packages 失效
标题翻译：电子骰子在组件包中自动定位的装置
公开(公告)号：US06900459B2
公开(公告)日：2005-05-31
申请号：US10310752
申请日：2002-12-05
申请人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
发明人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
IPC分类号： G01R31/26 , G01R31/28 , G01R31/311 , H01L21/00 , H01L21/60 , H01L21/66 , H01L21/68 , H05K13/08 , H01L23/58 , G01R31/02
CPC分类号： H01L21/67276 , G01R31/2851 , G01R31/2886 , G01R31/2893 , G01R31/311 , H01L21/67126 , H01L21/67242 , H01L21/67259 , H01L21/681 , H01L24/74 , H01L2924/12042 , H01L2924/14 , H05K13/08 , Y10T29/49004 , Y10T29/49131 , Y10T29/53174 , Y10T29/53178 , H01L2924/00
摘要： A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).
摘要翻译：从临时测试包的组件组装和拆卸要测试的半导体骰子的方法和装置。采用计算机控制的视觉系统将骰子与临时测试包基座对准，并且采用自动机器人手臂系统来检索和组装骰子与各种包装部件。本发明在骰子的老化和其他预包装测试中具有特殊的用途，以建立已知的骰子（KGD）。

29. 发明授权

US07589010B2 Semiconductor devices with permanent polymer stencil and method for manufacturing the same 有权
标题翻译：具有永久聚合物模板的半导体器件及其制造方法
公开(公告)号：US07589010B2
公开(公告)日：2009-09-15
申请号：US11210606
申请日：2005-08-23
申请人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Syed Sajid Ahmad , Michael E. Hess , John O. Jacobson
发明人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Syed Sajid Ahmad , Michael E. Hess , John O. Jacobson
IPC分类号： H01L21/44
CPC分类号： H01L23/544 , B33Y30/00 , B33Y80/00 , H01L21/563 , H01L23/293 , H01L23/3157 , H01L24/81 , H01L24/83 , H01L2223/5448 , H01L2224/05571 , H01L2224/05573 , H01L2224/11005 , H01L2224/1147 , H01L2224/11472 , H01L2224/16 , H01L2224/293 , H01L2224/81011 , H01L2224/8121 , H01L2224/81815 , H01L2224/83851 , H01L2924/00014 , H01L2924/01078 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/3512 , H01L2924/00 , H01L2224/05599
摘要： Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces of the semiconductor devices.
摘要翻译：使用具有孔的永久或临时聚合物层来制造半导体器件的方法来暴露接触焊盘并覆盖半导体器件的有源表面。

30. 发明授权

US06492187B1 Method for automatically positioning electronic die within component packages 失效
标题翻译：电子管芯在组件封装内自动定位的方法
公开(公告)号：US06492187B1
公开(公告)日：2002-12-10
申请号：US09651490
申请日：2000-08-30
申请人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
发明人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
IPC分类号： H01L2166
CPC分类号： H01L21/67276 , G01R31/2851 , G01R31/2886 , G01R31/2893 , G01R31/311 , H01L21/67126 , H01L21/67242 , H01L21/67259 , H01L21/681 , H01L24/74 , H01L2924/12042 , H01L2924/14 , H05K13/08 , Y10T29/49004 , Y10T29/49131 , Y10T29/53174 , Y10T29/53178 , H01L2924/00
摘要： A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).
摘要翻译：从临时测试包的组件组装和拆卸要测试的半导体骰子的方法和装置。采用计算机控制的视觉系统将骰子与临时测试包基座对准，并且采用自动机器人手臂系统来检索和组装骰子与各种包装部件。本发明在骰子的老化和其他预包装测试中具有特殊的用途，以建立已知的骰子（KGD）。

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