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21. 发明申请

US20060215677A1 Flexible control block format for frame description and management 失效
标题翻译：灵活的控制块格式，用于帧描述和管理
公开(公告)号：US20060215677A1
公开(公告)日：2006-09-28
申请号：US11091245
申请日：2005-03-28
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Philippe Damon , Joseph Logan , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Philippe Damon , Joseph Logan , Fabrice Verplanken
IPC分类号： H04L12/26 , H04L12/56
CPC分类号： H04L12/5601 , H04L49/90 , H04L2012/5642 , H04L2012/5652 , H04L2012/5658 , H04L2012/5681
摘要： A communication network used to link information handling systems together utilizes a switching network to transmit data among senders and receivers. Each individual packet of data is described and controlled by an FCB. The bandwidth associated with the storing and distribution of data is optimized by chaining the data packets in different types of queues, or operating without chaining outside a queue. When a frame is in an output queue, the third word contains an RFCBA for egress of the frame to a line port, and an MCID for ingress from an output queue to a switch port. The RFCBA and the MCID have multicast capabilities. The format does not require a third word when a frame is in an input queue.
摘要翻译：用于将信息处理系统链接在一起的通信网络利用交换网络在发送者和接收者之间传送数据。每个单独的数据包由FCB描述和控制。与存储和分发数据相关联的带宽通过将数据分组链接在不同类型的队列中进行优化，或者在不在队列外链接的情况下运行。当帧位于输出队列中时，第三个字包含用于将帧从线路端口排出的RFCBA，以及用于从输出队列进入交换机端口的MCID。 RFCBA和MCID具有多播功能。当帧在输入队列中时，格式不需要第三个字。

22. 发明授权

US6038592A Method and device of multicasting data in a communications system 失效
标题翻译：在通信系统中组播数据的方法和设备
公开(公告)号：US6038592A
公开(公告)日：2000-03-14
申请号：US635048
申请日：1996-04-19
申请人： Fabrice Verplanken , Claude Basso , Didier Giroir , Jean Calvignac , Claude Galand
发明人： Fabrice Verplanken , Claude Basso , Didier Giroir , Jean Calvignac , Claude Galand
IPC分类号： G06F13/00 , G06F15/16 , G06F15/177 , H04L12/18
CPC分类号： H04L12/18
摘要： An apparatus and method for multicasting messages stored in data buffers of a data storage. Each message is composed of data stored in a plurality of the data buffers. Each data buffer is controlled and mapped to a unique direct control block (DCB) which stores information characterizing the data buffer. By chaining the DCBs variable length, messages can be generated. Indirect control blocks (ICB) stores information characterizing the data or messages duplicated and points to a DCB. A field in the DCB carries a count representing the number of times the message is to be duplicated.
摘要翻译：一种用于组播存储在数据存储器的数据缓冲器中的消息的装置和方法。每个消息由存储在多个数据缓冲器中的数据组成。每个数据缓冲器被控制并映射到唯一的直接控制块（DCB），其存储表征数据缓冲器的信息。通过链接DCBs可变长度，可以生成消息。间接控制块（ICB）存储表征复制的数据或消息的信息，并指向DCB。 DCB中的字段表示消息被复制的次数。

23. 发明授权

US5794033A Method and system for in-site and on-line reprogramming of hardware logics with remote loading in a network device 失效
标题翻译：在网络设备中进行远程加载的硬件逻辑的现场和在线重新编程的方法和系统
公开(公告)号：US5794033A
公开(公告)日：1998-08-11
申请号：US547635
申请日：1995-10-24
申请人： Jeane-Paul Aldebert , Claude Basso , Jean Calvignac , Paul Chemla , Daniel Orsatti , Fabrice Verplanken , Jean-Claude Zunino
发明人： Jeane-Paul Aldebert , Claude Basso , Jean Calvignac , Paul Chemla , Daniel Orsatti , Fabrice Verplanken , Jean-Claude Zunino
IPC分类号： G06F13/38 , H03K19/177
CPC分类号： G06F13/4256
摘要： The invention discloses a method and an apparatus for in-line and on-site updating of Field Programmable Gate Arrays with remote loaded configuration data files. Flash EEPROMs which are used because of their non-volatile memories and their high density, are storing more than one configuration data file. The memories are divided in more than one part, each part of the memory for storing one configuration data file. One part of the memory also contains a flag identifying the currently loaded configuration data file. The Flash EPROM's bits being set to one same binary value before any writing operation, including the update of the configuration data file containing the flag. The setting of the bits to said binary value always identifies a valid other configuration data file in order to insure a correct re-loading of the FPGAs in case of reception of an unexpected event leading to an initialization.
摘要翻译：本发明公开了一种用于使用远程加载的配置数据文件进行现场可编程门阵列的在线和现场更新的方法和装置。由于其非易失性存储器及其高密度使用的闪存EEPROM存储多个配置数据文件。存储器分为多个部分，存储器的每个部分用于存储一个配置数据文件。存储器的一部分还包含标识当前加载的配置数据文件的标志。闪存EPROM的位在任何写入操作之前被设置为相同的二进制值，包括更新包含该标志的配置数据文件。对所述二进制值的位的设置总是标识有效的其他配置数据文件，以便在接收到导致初始化的意外事件的情况下确保正确地重新加载FPGA。

24. 发明申请

US20070067478A1 Data aligner in reconfigurable computing environment technical field 失效
标题翻译：数据对准器在可重构计算环境技术领域
公开(公告)号：US20070067478A1
公开(公告)日：2007-03-22
申请号：US11230956
申请日：2005-09-20
申请人： Fabrice Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Calvignac
发明人： Fabrice Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Calvignac
IPC分类号： G06F15/16
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译：公开了可重构计算环境中的数据对准器。实施例使用现场可配置门阵列（FPGA）中的硬件宏来最小化移动数据字节所需的可配置逻辑块（CLB）的数量。与专用集成电路相比，对准机制允许灵活性，可扩展性，可配置性和降低的成本。

25. 发明申请

US20060168583A1 Systems and methods for TDM multithreading 失效
标题翻译： TDM多线程的系统和方法
公开(公告)号：US20060168583A1
公开(公告)日：2006-07-27
申请号：US11042692
申请日：2005-01-25
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Gordon Davis , Harm Hofstee , Fabrice Verplanken , Colin Verrilli
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Gordon Davis , Harm Hofstee , Fabrice Verplanken , Colin Verrilli
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译：公开了用于在多线程数字处理器的流水线中分发线程指令的系统和方法。更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。如果要选择的线程无法执行，则选择补充线程执行。

26. 发明申请

US20060146881A1 Apparatus and method for efficiently modifying network data frames 失效
公开(公告)号：US20060146881A1
公开(公告)日：2006-07-06
申请号：US11030344
申请日：2005-01-06
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Fabrice Verplanken
IPC分类号： H04J3/00
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9021
摘要： Apparatus and method for storing network frame data which is to be modified. A plurality of buffers stores the network data which is arranged in a data structure identified by a frame control block and buffer control block. A plurality of buffer control blocks associated with each buffer storing the frame data establishes a sequence of the buffers. Each buffer control block has data for identifying a subsequent buffer within the sequence. The first buffer is identified by a field of a frame control block as well as the beginning and ending address of the frame data. The frame data can be modified without rewriting the data to memory by altering the buffer control block and/or frame control block contents without having to copy or rewrite the data in order to modify it.

27. 发明授权

US5444692A Token star bridge 失效
标题翻译：令牌星桥
公开(公告)号：US5444692A
公开(公告)日：1995-08-22
申请号：US161372
申请日：1993-12-02
申请人： Claude Basso , Jean Calvignac , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Fabrice Verplanken
IPC分类号： H04L12/433 , H04L12/56 , H04L12/417
CPC分类号： H04L12/433 , H04L49/3018 , H04L49/3027 , H04L49/351
摘要： The invention includes a bridge having n ports (n>1), each port being connected to a Token-Ring physical segment, each physical segment having one native Token-Ring workstation attached. The bridge to the workstations a single Token-Ring logical segment with a single Active Monitor and a single Ring Number. The invention includes a centralized medium access control (MAC) function inside a centralized processor instead of a MAC function implemented at each port of the bridge; the frame handling function, due to the fixed and limited configuration (same bridge Active Monitor seen by all connected stations), does not require a multi-port bridge function, but a simpler switch function between ports. Bridge clocking is also simplified, and a cost effective unshield twisted pair (UTP) retiming solution is presented.
摘要翻译：本发明包括具有n个端口（n> 1）的桥，每个端口连接到令牌环物理段，每个物理段具有一个本地令牌环工作站。工作站的桥接到单个活动监视器和单个环号的单个令牌环逻辑段。本发明包括集中式处理器内的中央媒体访问控制（MAC）功能，而不是在桥的每个端口处实现的MAC功能; 帧处理功能由于固定和限制配置（所有连接站所见的同一桥主动监视器）不需要多端口桥接功能，而是端口之间更简单的交换机功能。桥接时钟也被简化，并提出了一种经济有效的非屏蔽双绞线（UTP）重新定时器解决方案。

28. 发明申请

US20060101172A1 System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position 失效
标题翻译：网络处理器中的系统方法结构，通过最后一个标志位指示帧分组的最后数据缓冲区，处于第一或第二位置
公开(公告)号：US20060101172A1
公开(公告)日：2006-05-11
申请号：US11320277
申请日：2005-12-27
申请人： Claude Basso , Jean Calvignac , Marco Heddes , Joseph Logan , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Marco Heddes , Joseph Logan , Fabrice Verplanken
IPC分类号： G06F5/00
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3018 , H04L49/90 , H04L49/9094
摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.
摘要翻译：提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器的特定框架。

29. 发明申请

US20050177644A1 Structure and method for scheduler pipeline design for hierarchical link sharing 失效
标题翻译：用于分层链路共享的调度器流水线设计的结构和方法
公开(公告)号：US20050177644A1
公开(公告)日：2005-08-11
申请号：US10772737
申请日：2004-02-05
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Gordon Davis , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Gordon Davis , Fabrice Verplanken
IPC分类号： G06F15/16 , H04L12/56
CPC分类号： H04L47/60 , H04L47/15 , H04L47/50 , H04L47/52 , H04L49/90
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译：描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。该配置通过最小化外部SRAM存储器件的使用来降低成本。这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

30. 发明授权

US5787071A Hop-by-hop flow control in an ATM network 失效
标题翻译： ATM网络中的逐跳流量控制
公开(公告)号：US5787071A
公开(公告)日：1998-07-28
申请号：US554113
申请日：1995-11-06
申请人： Claude Basso , Jean Calvignac , Daniel Orsatti , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Daniel Orsatti , Fabrice Verplanken
IPC分类号： H04Q3/00 , H04L12/56 , H04Q11/04
CPC分类号： H04L12/5602 , H04Q11/0478 , H04L2012/5619 , H04L2012/563 , H04L2012/5632 , H04L2012/5635 , H04L2012/5636 , H04L2012/5651 , H04L2012/5652
摘要： A communication system comprises a plurality of nodes interconnected by links comprising a plurality of connections. The traffic between the nodes is set up by a reserved bandwidth service and/or a non reserved bandwidth service. The non reserved bandwidth service is controlled by a hop by hop backpressure mechanism. When the traffic entering a node exceeds a high threshold, the backpressure mechanism generates stop backpressure primitives in order to throttle the entering traffic. In case of congestion the mechanism is either able to selectively interuppt the connection contributing to the congestion without affecting the rest of the link traffic, or to globally stop all link traffic. Traffic can be resumed if traffic rates fall below the low threshold values.
摘要翻译：通信系统包括通过包括多个连接的链路互连的多个节点。节点之间的流量由保留的带宽服务和/或非保留带宽服务建立。非保留带宽服务由逐跳背压机制控制。当进入节点的流量超过高阈值时，背压机制产生停止背压原语，以节流输入流量。在拥塞的情况下，该机制能够选择性地插入有助于拥塞的连接而不影响链路业务的其余部分，或全局地停止所有链路业务。如果流量低于低阈值，流量可以恢复。

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