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21. 发明授权

US08030181B2 Electrical fuse circuit for security applications 有权
标题翻译：电熔丝电路用于安全应用
公开(公告)号：US08030181B2
公开(公告)日：2011-10-04
申请号：US12881944
申请日：2010-09-14
申请人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
发明人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
IPC分类号： H01L21/326
CPC分类号： G11C17/18
摘要： A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.
摘要翻译：公开了一种熔丝电路，其包括至少一个电熔丝元件，该电熔丝元件具有在电迁移模式下受到应力之后变化的电阻;开关装置，其在熔丝编程电源（VDDQ）之间的预定路径中与电熔丝元件串联连接，以及用于在编程操作期间选择性地允许通过电熔丝元件的编程电流的低电压电源（GND），以及耦合到所述VDDQ的至少一个外围电路，其中所述外围电路是有效的并且在VDDQ期间从VDDQ引出电流保险丝编程操作。

22. 发明申请

US20080283963A1 Electrical Fuse Circuit for Security Applications 有权
标题翻译：用于安全应用的电保险电路
公开(公告)号：US20080283963A1
公开(公告)日：2008-11-20
申请号：US11748959
申请日：2007-05-15
申请人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
发明人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
IPC分类号： H01L23/62 , H01L29/00
CPC分类号： G11C17/18
摘要： A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.
摘要翻译：公开了一种熔丝电路，其包括至少一个电熔丝元件，该电熔丝元件具有在电迁移模式下受到应力之后变化的电阻;开关装置，其在熔丝编程电源（VDDQ）之间的预定路径中与电熔丝元件串联连接，以及用于在编程操作期间选择性地允许通过电熔丝元件的编程电流的低电压电源（GND），以及耦合到所述VDDQ的至少一个外围电路，其中所述外围电路是有效的并且在VDDQ期间从VDDQ引出电流保险丝编程操作。

23. 发明授权

US07323379B2 Fabrication process for increased capacitance in an embedded DRAM memory 失效
标题翻译：嵌入式DRAM存储器中增加电容的制造工艺
公开(公告)号：US07323379B2
公开(公告)日：2008-01-29
申请号：US11050988
申请日：2005-02-03
申请人： Dennis Sinitsky , Fu-Chieh Hsu
发明人： Dennis Sinitsky , Fu-Chieh Hsu
IPC分类号： H01L21/8238
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/11
摘要： An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-dielectric-semiconductor (MOS) capacitor in a deep trench isolation region. A cavity is formed in the deep trench isolation, thereby exposing a sidewall region of the substrate. The sidewall region is doped, thereby forming one electrode of the cell capacitor. A gate dielectric layer is formed over the exposed sidewall, and a polysilicon layer is deposited over the resulting structure, thereby filling the cavity. The polysilicon layer is patterned to form the gate electrode of the access transistor and a capacitor electrode, which extends over the sidewall region and upper surface of the substrate.
摘要翻译：嵌入式存储器系统包括与深沟槽隔离隔离的动态随机存取存储器（DRAM）单元阵列和与浅沟槽隔离隔离的逻辑晶体管。每个DRAM单元包括存取晶体管和电容器结构。通过在深沟槽隔离区域中形成金属 - 电介质半导体（MOS）电容器来制造电容器结构。在深沟槽隔离中形成空腔，从而暴露衬底的侧壁区域。侧壁区域被掺杂，从而形成单元电容器的一个电极。在暴露的侧壁上形成栅介电层，并且在所得结构上沉积多晶硅层，从而填充空腔。图案化多晶硅层以形成存取晶体管的栅电极和在衬底的侧壁区域和上表面上延伸的电容器电极。

24. 发明申请

US20060172504A1 Fabrication process for increased capacitance in an embedded DRAM memory 失效
标题翻译：嵌入式DRAM存储器中增加电容的制造工艺
公开(公告)号：US20060172504A1
公开(公告)日：2006-08-03
申请号：US11050988
申请日：2005-02-03
申请人： Dennis Sinitsky , Fu-Chieh Hsu
发明人： Dennis Sinitsky , Fu-Chieh Hsu
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/11
摘要： An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-dielectric-semiconductor (MOS) capacitor in a deep trench isolation region. A cavity is formed in the deep trench isolation, thereby exposing a sidewall region of the substrate. The sidewall region is doped, thereby forming one electrode of the cell capacitor. A gate dielectric layer is formed over the exposed sidewall, and a polysilicon layer is deposited over the resulting structure, thereby filling the cavity. The polysilicon layer is patterned to form the gate electrode of the access transistor and a capacitor electrode, which extends over the sidewall region and upper surface of the substrate.
摘要翻译：嵌入式存储器系统包括与深沟槽隔离隔离的动态随机存取存储器（DRAM）单元阵列和与浅沟槽隔离隔离的逻辑晶体管。每个DRAM单元包括存取晶体管和电容器结构。通过在深沟槽隔离区域中形成金属 - 电介质半导体（MOS）电容器来制造电容器结构。在深沟槽隔离中形成空腔，从而暴露衬底的侧壁区域。侧壁区域被掺杂，从而形成单元电容器的一个电极。在暴露的侧壁上形成栅介电层，并且在所得结构上沉积多晶硅层，从而填充空腔。图案化多晶硅层以形成存取晶体管的栅电极和在衬底的侧壁区域和上表面上延伸的电容器电极。

25. 发明授权

US07056785B2 Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same 失效
公开(公告)号：US07056785B2
公开(公告)日：2006-06-06
申请号：US10999259
申请日：2004-11-29
申请人： Fu-Chieh Hsu
发明人： Fu-Chieh Hsu
IPC分类号： H01L21/8242
CPC分类号： H01L27/11521 , G11C7/20 , G11C16/0416 , G11C2216/10 , H01L21/28273 , H01L27/11558 , H01L29/66825
摘要： A non-volatile memory cell is fabricated using a conventional logic process, with minor modifications. The cell is fabricated by forming a shallow trench isolation (STI) region in a well region of a semiconductor substrate. A recessed region is formed in the STI region, wherein the recessed region extends into the STI region and exposes a sidewall region in the well region. A capacitor region is formed in the sidewall region. A dielectric layer is formed over the well region, including the sidewall region. A gate electrode is then formed over the dielectric layer, wherein a portion of the gate electrode extends into the recessed region. An access transistor of the cell is then formed in a self-aligned manner with respect to the gate electrode. A capacitor structure is formed by the gate electrode (in the recessed region), the dielectric layer on the sidewall region, and the capacitor region.

26. 发明授权

US06661042B2 One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region 失效
标题翻译：具有电隔离电荷存储区域的大容量CMOS工艺中的单晶体管浮体DRAM单元
公开(公告)号：US06661042B2
公开(公告)日：2003-12-09
申请号：US10095901
申请日：2002-03-11
申请人： Fu-Chieh Hsu
发明人： Fu-Chieh Hsu
IPC分类号： H01L29768
CPC分类号： H01L27/108 , H01L27/0214 , H01L27/10802 , H01L27/10873 , H01L29/7841
摘要： A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region. A buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region. A bias voltage can be applied to the buried region, thereby controlling leakage currents in the 1T/FB DRAM cell.
摘要翻译：提供了一个单晶体管浮体（1T / FB）动态随机存取存储器（DRAM）单元，其包括使用与标准CMOS工艺兼容的工艺制造的场效应晶体管。场效应晶体管包括位于源极区域和漏极区域之间的第一导电类型的源极区域和漏极区域以及与第一导电类型相反的第二导电类型的浮动体区域。第一导电类型的掩埋区域位于源极区域，漏极区域和浮体区域的下方。掩埋区域有助于形成耗尽区，其位于掩埋区域与源极区域，漏极区域和浮体区域之间。浮体区由此被耗尽区隔离。可以将偏置电压施加到掩埋区域，从而控制1T / FB DRAM单元中的漏电流。

27. 发明授权

US06573548B2 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same 有权
公开(公告)号：US06573548B2
公开(公告)日：2003-06-03
申请号：US10033690
申请日：2001-11-02
申请人： Wingyu Leung , Fu-Chieh Hsu
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： H01L31112
CPC分类号： H01L27/1085 , G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , G11C2207/104 , H01L21/76895 , H01L27/0214 , H01L27/10835 , H01L27/10852 , H01L27/10873 , H01L28/86 , H01L28/91
摘要： A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.

28. 发明授权

US06457108B1 Method of operating a system-on-a-chip including entering a standby state in a non-volatile memory while operating the system-on-a-chip from a volatile memory 有权
标题翻译：操作片上系统的方法，包括在易失性存储器中操作片上系统的同时在非易失性存储器中进入待机状态
公开(公告)号：US06457108B1
公开(公告)日：2002-09-24
申请号：US09415032
申请日：1999-10-07
申请人： Fu-Chieh Hsu , Wingyu Leung
发明人： Fu-Chieh Hsu , Wingyu Leung
IPC分类号： G06F1300
CPC分类号： H01L27/11521 , G11C7/20 , G11C16/0416 , G11C2216/10 , H01L21/28273 , H01L27/11558 , H01L29/66825
摘要： A method of operating a system-on-a-chip having a logic circuit and a thin-oxide non-volatile memory embedded or located on a single chip. In this method, the contents of the non-volatile memory cells are read out and stored (with or without data decompression operations) into on-chip or off-chip volatile memory. The data contents of the non-volatile memory cells are then refreshed (through charge injection and removal) with optimum signal condition. The non-volatile memory cells then remain in an idle or standby mode substantially without a significant external electric field, while the system-on-a-chip is operated in response to the data stored in the volatile memory. If a reprogramming operation or a refresh operation is required, then the non-volatile memory cells are reprogrammed or refreshed as required and then returned to the idle or standby mode. As a result, the storage characteristics of the non-volatile memory cells are improved.
摘要翻译：一种操作片上系统的方法，其具有嵌入或位于单个芯片上的逻辑电路和薄氧化物非易失性存储器。在该方法中，将非易失性存储单元的内容读出并存储（具有或不具有数据解压缩操作）到片上或片外易失性存储器中。然后通过最佳信号条件刷新非易失性存储单元的数据内容（通过电荷注入和去除）。然后，非易失性存储器单元基本上没有显着的外部电场而保持在空闲或待机模式，同时在片上系统响应于存储在易失性存储器中的数据而被操作。如果需要重新编程操作或刷新操作，则根据需要对非易失性存储单元进行重新编程或刷新，然后返回到空闲或待机模式。结果，提高了非易失性存储单元的存储特性。

29. 发明授权

US06425046B1 Method for using a latched sense amplifier in a memory module as a high-speed cache memory 失效
标题翻译：将存储器模块中的锁存读出放大器用作高速缓存存储器的方法
公开(公告)号：US06425046B1
公开(公告)日：2002-07-23
申请号：US08820297
申请日：1997-03-18
申请人： Wing Yu Leung , Fu-Chieh Hsu
发明人： Wing Yu Leung , Fu-Chieh Hsu
IPC分类号： G11C700
CPC分类号： H04L25/0272 , G06F11/006 , G06F11/10 , G06F11/1032 , G06F11/2007 , G06F12/0661 , G06F13/4077 , G11C5/04 , G11C29/006 , G11C29/08 , G11C29/48 , G11C29/76 , G11C29/808 , G11C29/81 , G11C29/832 , G11C29/88 , G11C2029/0401 , G11C2029/0411 , G11C2029/4402 , H01L22/22 , H01L27/0203 , H04L5/1461 , H04L25/026 , H04L25/028 , H04L25/029 , H04L25/0292 , Y10S257/907
摘要： A fault-tolerant, high-speed wafer scale system includes a plurality of functional memory modules, each having associated sense amplifiers which act as high-speed cache memory, a parallel hierarchical bus which is fault-tolerant to defects and a interconnect network, and one or more bus masters. By grouping the DRAM arrays into logically independent modules of relatively small memory capacity (588 Kbit), a large number of cache lines (128) is obtained at small main memory capacity (4 Megabytes). The large number of cache lines allows maintaining a high cache hit rate (greater than 90%).
摘要翻译：容错的高速晶片刻度系统包括多个功能存储器模块，每个功能存储器模块具有作为高速高速缓冲存储器的相关联的读出放大器，对缺陷容错的并行分层总线和互连网络，以及一个或多个巴士主人。通过将DRAM阵列分组成具有相对小的存储容量（588Kbit）的逻辑上独立的模块，在小的主存储器容量（4兆字节）下获得大量的高速缓存行（128）。大量的缓存行允许保持高缓存命中率（大于90％）。

30. 发明授权

US06295593B1 Method of operating memory array with write buffers and related apparatus 有权
标题翻译：使用写入缓冲器和相关设备操作存储器阵列的方法
公开(公告)号：US06295593B1
公开(公告)日：2001-09-25
申请号：US09153099
申请日：1998-09-14
申请人： Fu-Chieh Hsu , Wingyu Leung
发明人： Fu-Chieh Hsu , Wingyu Leung
IPC分类号： G06F1206
CPC分类号： G06F12/0893 , G06F12/0855 , G06F12/0879 , G06F12/0897 , G06F12/10 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/406 , G11C11/4076 , G11C11/4096
摘要： A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and a second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, the precharging of the DRAM array is transparent to the CPU bus. A structure and method control the refresh and internal operations of the DRAM array.
摘要翻译：一种用于在计算机系统中实现DRAM存储器阵列作为第二级高速缓冲存储器的方法和结构。计算机系统包括中央处理单元（CPU），第一级SRAM缓存存储器，耦合到CPU的CPU总线，以及包括连接到CPU总线的DRAM阵列的第二级高速缓冲存储器。当访问DRAM阵列时，以自定时的异步方式执行行访问和列解码操作。然后以相对于时钟信号的同步方式执行列选择操作的预定序列。向DRAM阵列提供加宽的数据路径，有效地增加DRAM阵列的数据速率。通过以比CPU总线更高的数据速率操作DRAM阵列，为DRAM阵列预充电提供了额外的时间。结果，DRAM阵列的预充电对CPU总线是透明的。一种结构和方法来控制DRAM阵列的刷新和内部操作。

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