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21. 发明申请

US20070215939A1 Quasi-vertical LDMOS device having closed cell layout 有权
标题翻译：具有闭孔布局的准垂直LDMOS器件
公开(公告)号：US20070215939A1
公开(公告)日：2007-09-20
申请号：US11376470
申请日：2006-03-14
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L29/0692 , H01L29/0878 , H01L29/0886 , H01L29/1045 , H01L29/4175 , H01L29/4238 , H01L29/7802 , H01L29/7835
摘要： A low voltage power device includes a plurality of quasi-vertical LDMOS device cells. A conductive trench sinker is formed through the epitaxial layer and adjacent a selected one of the source and drain regions in each cell. The trench sinker electrically couples the selected one of the source and drain regions to the substrate for coupling current from the channel to the substrate. The resulting device exhibits a vertical current flow between the metal electrode covering the front surface and the second electrode formed at the back side of the wafer. The device cells are arranged in a closed cell configuration.
摘要翻译：低压功率器件包括多个准垂直LDMOS器件单元。导电沟槽沉积片通过外延层形成并且与每个单元中的源极和漏极区域中的一个相邻。沟槽沉积片将所选择的源极和漏极区之一电耦合到衬底，以将电流从沟道耦合到衬底。所得到的器件在覆盖前表面的金属电极和形成在晶片背面的第二电极之间呈现垂直的电流。设备单元被布置成闭孔配置。

22. 发明申请

US20070085204A1 Chip scale power LDMOS device 有权
标题翻译：芯片级功率LDMOS器件
公开(公告)号：US20070085204A1
公开(公告)日：2007-04-19
申请号：US11254482
申请日：2005-10-19
申请人： Jacek Korec , Shuming Xu , Wenhua Dai
发明人： Jacek Korec , Shuming Xu , Wenhua Dai
IPC分类号： H01L23/48
CPC分类号： H01L24/13 , H01L24/14 , H01L29/0653 , H01L29/0847 , H01L29/0873 , H01L29/0878 , H01L29/0882 , H01L29/4175 , H01L29/41766 , H01L29/4933 , H01L29/7816 , H01L29/7835 , H01L2224/05001 , H01L2224/13 , H01L2224/13028 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/014 , H01L2924/12036 , H01L2924/1306 , H01L2924/13091 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： A semiconductor device includes at least one macro-cell device, the macro-cell device comprising a plurality of LDMOS devices. A first conductive layer is formed over the substrate, the first conductive layer providing source and drain contacts for the macro-cell device. A first isolation layer is formed over the first conductive layer and a second conductive layer is formed over the first isolation layer, the second conductive layer forming a drain bus and a source bus, wherein the buses are electrically coupled to the contacts through the first isolation layer. A second isolation layer is formed over the second conductive layer and insulates the source bus from the drain bus. A plurality of conductive bumps are formed over the second isolation layer, at least one of the conductive bumps directly contacting the drain bus and at least one of the conductive bumps directly contacting the source bus through the second isolation layer.
摘要翻译：半导体器件包括至少一个宏小区设备，该宏小区设备包括多个LDMOS设备。第一导电层形成在衬底上，第一导电层提供用于宏电池器件的源极和漏极接触。在第一导电层上形成第一隔离层，在第一隔离层上形成第二导电层，第二导电层形成漏极总线和源极总线，其中总线通过第一隔离电耦合到触点层。在第二导电层上形成第二隔离层，并将源极总线与漏极母线绝缘。多个导电凸块形成在第二隔离层上方，至少一个导电凸块直接接触漏极母线和至少一个导电凸块直接通过第二隔离层与源极总线接触。

23. 发明申请

US20070034944A1 Power LDMOS transistor 有权
公开(公告)号：US20070034944A1
公开(公告)日：2007-02-15
申请号：US11202968
申请日：2005-08-12
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L29/94 , H01L31/00 , H01L29/76
CPC分类号： H01L29/7835 , H01L29/1083 , H01L29/1087 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/4933
摘要： A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device includes a doped substrate having an epitaxial layer thereover having source and drain implant regions and body and lightly doped drain regions formed therein. The channel region and lightly doped drain regions are doped to a depth to abut the top surface of the substrate. In alternative embodiments, a buffer region of the second conductivity type and having dopant concentration greater than or equal to about the channel region is formed over the top surface of the substrate between the top surface of the substrate and the channel region and lightly doped drain region, wherein the channel region and lightly doped drain regions are doped to a depth to abut the buffer region.

24. 发明申请

US20080054994A1 Dual-Gate Metal-Oxide-Semiconductor Device 失效
标题翻译：双栅极金属氧化物半导体器件
公开(公告)号：US20080054994A1
公开(公告)日：2008-03-06
申请号：US11927950
申请日：2007-10-30
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： G05F1/10 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7835 , H01L29/402 , H01L29/7831
摘要： An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region of the first conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on the upper surface of the semiconductor layer. A first gate is formed on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region, and at least a second gate formed on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region. The second gate has a length which is substantially greater than a length of the first gate, the first and second gates being electrically isolated from one another.
摘要翻译： MOS器件包括在半导体层的上表面附近形成在第二导电类型的半导体层中的第一导电类型的第一和第二源极/漏极区域，第一和第二源极/漏极区域相对于彼此间隔开。第一导电类型的非均匀掺杂沟道区形成在靠近半导体层的上表面的半导体层中，并且至少部分地在第一和第二源/漏区之间。绝缘层形成在半导体层的上表面上。至少部分地在第一和第二源极/漏极区域之间并且在沟道区域的至少一部分上方形成第一栅极，并且至少在绝缘层上形成的至少一部分第二栅极并且在第一栅极和第二源极/漏极区域之间。第二栅极的长度远大于第一栅极的长度，第一栅极和第二栅极彼此电隔离。

25. 发明授权

US07297606B2 Metal-oxide-semiconductor device including a buried lightly-doped drain region 有权
标题翻译：金属氧化物半导体器件包括埋入的轻掺杂漏极区域
公开(公告)号：US07297606B2
公开(公告)日：2007-11-20
申请号：US11116903
申请日：2005-04-28
申请人： Muhammed Ayman Shibib , Shuming Xu
发明人： Muhammed Ayman Shibib , Shuming Xu
IPC分类号： H01L21/336
CPC分类号： H01L29/402 , H01L29/0615 , H01L29/0847 , H01L29/0873 , H01L29/4175 , H01L29/66659 , H01L29/7835
摘要： An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.
摘要翻译： MOS器件包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的源极区和形成在半导体层中并与源极区隔开的第二导电类型的漏极区。栅极形成在半导体层的上表面附近，并且至少部分地在源区和漏区之间形成。 MOS器件还包括形成在栅极和漏极区域之间的半导体层中的第二导电类型的埋入LDD区域，所述掩埋LDD区域与漏极区域横向间隔开，并且形成第一导电类型的第二LDD区域在掩埋的LDD区域中并且靠近半导体层的上表面。第二LDD区域与栅极自对准并且与栅极横向隔开，使得栅极相对于第二LDD区域不重叠。

26. 发明申请

US20060071270A1 Metal-oxide-semiconductor device having trenched diffusion region and method of forming same 审中-公开
标题翻译：具有沟槽扩散区域的金属氧化物半导体器件及其形成方法
公开(公告)号：US20060071270A1
公开(公告)日：2006-04-06
申请号：US10953018
申请日：2004-09-29
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L21/223 , H01L21/2253 , H01L21/266 , H01L29/0653 , H01L29/0657 , H01L29/0886 , H01L29/1037 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.
摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的靠近半导体层的上表面的第二导电类型的第一和第二源极/漏极区域。第一和第二源极/漏极区域相对于彼此间隔开。至少部分地在第一和第二源极/漏极区之间形成栅极，并与半导体层电隔离。第一和第二源极/漏极区域中的至少一个被配置为具有基本上大于半导体层和给定源极/漏极区域之间的结的宽度的有效宽度。

27. 发明申请

US20050285189A1 Graded conductive structure for use in a metal-oxide-semiconductor device 有权
标题翻译：用于金属氧化物半导体器件的分级导电结构
公开(公告)号：US20050285189A1
公开(公告)日：2005-12-29
申请号：US10878857
申请日：2004-06-28
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L21/336 , H01L29/08 , H01L29/40 , H01L29/417 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7816 , H01L29/0847 , H01L29/402 , H01L29/404 , H01L29/4175 , H01L29/41758 , H01L29/41775 , H01L29/66659 , H01L29/7802 , H01L29/7835
摘要： An MOS device comprises a semiconductor layer of a first conductivity type and source and drain regions of a second conductivity type formed in the semiconductor layer, the source and drain regions being spaced apart from one another. A drift region is formed in the semiconductor layer proximate an upper surface of the semiconductor layer and between the source and drain regions, and a insulating layer is formed on the semiconductor layer above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the source and drift regions. The MOS device further includes a conductive structure comprising a first end formed on the insulating layer and spaced apart from the gate, and a second end formed on the insulating layer and extending laterally toward the drain region above at least a portion of the drift region. The conductive structure is configured such that a thickness of the insulating layer under the second end of the conductive structure increases as the second end extends toward the drain region.
摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的第二导电类型的源区和漏区，源极和漏极彼此间隔开。在半导体层中，靠近半导体层的上表面并且在源极和漏极区之间形成漂移区，并且在漂移区的至少一部分上方的半导体层上形成绝缘层。栅极形成在绝缘层上并且至少部分地在源极和漂移区域之间。 MOS器件还包括导电结构，该导电结构包括形成在绝缘层上并与栅极隔开的第一端，以及形成在绝缘层上并在漂移区的至少一部分上方向漏极区横向延伸的第二端。导电结构被构造成使得当导电结构的第二端下方的绝缘层的厚度随着第二端向漏极区延伸而增加。

28. 发明申请

US20120175702A1 METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING TRENCHED DIFFUSION REGION AND METHOD OF FORMING SAME 有权
标题翻译：具有扩张扩张区域的金属氧化物半导体器件及其形成方法
公开(公告)号：US20120175702A1
公开(公告)日：2012-07-12
申请号：US13428540
申请日：2012-03-23
申请人： Muhammed Ayman Shibib , Shuming Xu
发明人： Muhammed Ayman Shibib , Shuming Xu
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/223 , H01L21/2253 , H01L21/266 , H01L29/0653 , H01L29/0657 , H01L29/0886 , H01L29/1037 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.
摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的靠近半导体层的上表面的第二导电类型的第一和第二源极/漏极区域。第一和第二源极/漏极区域相对于彼此间隔开。至少部分地在第一和第二源极/漏极区之间形成栅极，并与半导体层电隔离。第一和第二源极/漏极区域中的至少一个被配置为具有基本上大于半导体层和给定源极/漏极区域之间的结的宽度的有效宽度。

29. 发明申请

US20080093667A1 Metal-oxide-semiconductor device having trenched diffusion region and method of forming same 有权
标题翻译：具有沟槽扩散区域的金属氧化物半导体器件及其形成方法
公开(公告)号：US20080093667A1
公开(公告)日：2008-04-24
申请号：US11999168
申请日：2007-12-04
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/223 , H01L21/2253 , H01L21/266 , H01L29/0653 , H01L29/0657 , H01L29/0886 , H01L29/1037 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.
摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的靠近半导体层的上表面的第二导电类型的第一和第二源极/漏极区域。第一和第二源极/漏极区域相对于彼此间隔开。至少部分地在第一和第二源极/漏极区之间形成栅极，并与半导体层电隔离。第一和第二源极/漏极区域中的至少一个被配置为具有基本上大于半导体层和给定源极/漏极区域之间的结的宽度的有效宽度。

30. 发明授权

US07329922B2 Dual-gate metal-oxide semiconductor device 有权
标题翻译：双栅极金属氧化物半导体器件
公开(公告)号：US07329922B2
公开(公告)日：2008-02-12
申请号：US10999705
申请日：2004-11-30
申请人： Muhammed Ayman Shibib , Shuming Xu
发明人： Muhammed Ayman Shibib , Shuming Xu
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7835 , H01L29/402 , H01L29/7831
摘要： An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region of the first conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on the upper surface of the semiconductor layer. A first gate is formed on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region, and at least a second gate formed on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region. The second gate has a length which is substantially greater than a length of the first gate, the first and second gates being electrically isolated from one another.
摘要翻译： MOS器件包括在半导体层的上表面附近形成在第二导电类型的半导体层中的第一导电类型的第一和第二源极/漏极区域，第一和第二源极/漏极区域相对于彼此间隔开。第一导电类型的非均匀掺杂沟道区形成在靠近半导体层的上表面的半导体层中，并且至少部分地在第一和第二源/漏区之间。绝缘层形成在半导体层的上表面上。至少部分地在第一和第二源极/漏极区域之间并且在沟道区域的至少一部分上方形成第一栅极，并且至少在绝缘层上形成的至少一部分第二栅极并且在第一栅极和第二源极/漏极区域之间。第二栅极的长度远大于第一栅极的长度，第一栅极和第二栅极彼此电隔离。

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