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21. 发明授权

US06894937B2 Accelerated life test of MRAM cells 失效
标题翻译： MRAM细胞加速寿命试验
公开(公告)号：US06894937B2
公开(公告)日：2005-05-17
申请号：US10672959
申请日：2003-09-26
申请人： Bradley J. Garni , Thomas W. Andre , Joseph J. Nahas
发明人： Bradley J. Garni , Thomas W. Andre , Joseph J. Nahas
IPC分类号： G11C11/15 , G11C29/50 , G11C29/00
CPC分类号： G11C29/50 , G11C11/16 , G11C2029/5002
摘要： A circuit provides a stress voltage to magnetic tunnel junctions (MTJs), which comprise the storage elements of a magnetoresitive random access memory (MRAM), during an accelerated life test of the MRAM. The stress voltage is selected to provide a predetermined acceleration of aging compared to normal operation. A source follower circuit is used to apply a stress voltage to a subset of the memory cells at given point in time during the life test. The stress voltage is maintained at the desired voltage by a circuit that mocks the loading characteristics of the portion of the memory array being stressed. The result is a closely defined voltage applied to the MTJs so that the magnitude of the acceleration is well defined for all of the memory cells.
摘要翻译：在MRAM的加速寿命测试期间，电路向包括磁阻随机存取存储器（MRAM）的存储元件的磁隧道结（MTJ）提供应力电压。选择应力电压以提供与正常操作相比预定的老化加速度。源极跟随器电路用于在寿命测试期间的给定时间点将应力电压施加到存储器单元的子集。应力电压通过嘲笑存储器阵列部分的负载特性受到应力的电路保持在所需电压。结果是施加到MTJ的紧密定义的电压，使得对于所有存储器单元良好地限定加速度的大小。

22. 发明授权

US06888743B2 MRAM architecture 有权
标题翻译： MRAM架构
公开(公告)号：US06888743B2
公开(公告)日：2005-05-03
申请号：US10331058
申请日：2002-12-27
申请人： Mark A. Durlam , Thomas W. Andre , Brian R. Butcher , Mark F. Deherrera , Bradley N. Engel , Bradley J. Garni , Gregory W. Grynkewich , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani , Clarance J. Tracy
发明人： Mark A. Durlam , Thomas W. Andre , Brian R. Butcher , Mark F. Deherrera , Bradley N. Engel , Bradley J. Garni , Gregory W. Grynkewich , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani , Clarance J. Tracy
IPC分类号： G11C11/15 , G11C11/02
CPC分类号： G11C11/16
摘要： An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.
摘要翻译：提供了一种减少隔离晶体管数量的MRAM架构。 MRAM架构包括电耦合以形成有组合的存储单元的磁阻存储单元。组合存储单元的磁阻存储单元由磁隧道结（MTJ）形成，并且形成为没有隔离器件，例如隔离晶体管，并且编程线和位线与每个磁阻存储器单元相邻。优选地，联动存储单元的磁阻存储单元仅包括MTJ，并且编程线和位线与每个磁阻存储单元相邻。

23. 发明授权

US07532533B2 Antifuse circuit and method for selectively programming thereof 有权
标题翻译：防腐电路及其选择性编程方法
公开(公告)号：US07532533B2
公开(公告)日：2009-05-12
申请号：US11737506
申请日：2007-04-19
申请人： Thomas W. Andre , Chitra K. Subramanian
发明人： Thomas W. Andre , Chitra K. Subramanian
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C11/1673 , G11C11/1695 , G11C11/5692 , G11C17/02
摘要： An antifuse circuit provides on a per bit basis a signal that indicates whether an MTJ (magnetic tunnel junction) antifuse has been previously programmed to a low resistance state in response to a program voltage. A sense amplifier provides the resistance state signal. A plurality of reference magnetic tunnel junctions are coupled in parallel and to the sense amplifier, each having a resistance within a range to provide a collective resistance that can be determined by the sense amplifier to differ from each resistance state of the MTJ antifuse. A write circuit selectively provides a current sufficient to create the program voltage when the write circuit is enabled to program the antifuse magnetic tunnel junction. Upon detecting a change in resistance in the MTJ antifuse, the write circuit reduces current supplied to the antifuse. Multiple antifuses may be programmed concurrently. Gate oxide thicknesses of transistors are adjusted for optimal performance.
摘要翻译：反熔丝电路以每比特为基础提供一个信号，该信号指示MTJ（磁性隧道结）反熔丝是否已经被预先编程为响应于编程电压的低电阻状态。读出放大器提供电阻状态信号。多个参考磁隧道结并联耦合到读出放大器，每个具有一个范围内的电阻，以提供可由感测放大器确定的不同于MTJ反熔丝的每个电阻状态的集合电阻。写入电路选择性地提供足以在写入电路被编程反熔丝磁性隧道结时产生编程电压的电流。当检测到MTJ反熔丝中的电阻变化时，写入电路减少提供给反熔丝的电流。多个反熔丝可以同时编程。调整晶体管的栅极氧化物厚度以获得最佳性能。

24. 发明授权

US07224630B2 Antifuse circuit 有权
标题翻译：防腐电路
公开(公告)号：US07224630B2
公开(公告)日：2007-05-29
申请号：US11166139
申请日：2005-06-24
申请人： Thomas W. Andre , Chitra K. Subramanian
发明人： Thomas W. Andre , Chitra K. Subramanian
IPC分类号： G11C7/02
CPC分类号： G11C17/18 , G11C11/1673 , G11C11/1695 , G11C11/5692 , G11C17/02
摘要： An antifuse circuit provides on a per bit basis a signal that indicates whether an MTJ (magnetic tunnel junction) antifuse has been previously programmed to a low resistance state in response to a program voltage. A sense amplifier provides the resistance state signal. A plurality of reference magnetic tunnel junctions are coupled in parallel and to the sense amplifier, each having a resistance within a range to provide a collective resistance that can be determined by the sense amplifier to differ from each resistance state of the MTJ antifuse. A write circuit selectively provides a current sufficient to create the program voltage when the write circuit is enabled to program the antifuse magnetic tunnel junction. Upon detecting a change in resistance in the MTJ antifuse, the write circuit reduces current supplied to the antifuse. Multiple antifuses may be programmed concurrently. Gate oxide thicknesses of transistors are adjusted for optimal performance.
摘要翻译：反熔丝电路以每比特为基础提供一个信号，该信号指示MTJ（磁性隧道结）反熔丝是否已经被预先编程为响应于编程电压的低电阻状态。读出放大器提供电阻状态信号。多个参考磁隧道结并联耦合到读出放大器，每个具有在一个范围内的电阻，以提供可由感测放大器确定的不同于MTJ反熔丝的每个电阻状态的集合电阻。写入电路选择性地提供足以在写入电路被编程反熔丝磁性隧道结时产生编程电压的电流。当检测到MTJ反熔丝中的电阻变化时，写入电路减少提供给反熔丝的电流。多个反熔丝可以同时编程。调整晶体管的栅极氧化物厚度以获得最佳性能。

25. 发明授权

US07292484B1 Sense amplifier with multiple bits sharing a common reference 有权
标题翻译：具有多个位的感应放大器共享一个共同的参考
公开(公告)号：US07292484B1
公开(公告)日：2007-11-06
申请号：US11422774
申请日：2006-06-07
申请人： Thomas W. Andre , Brad J. Garni , Joseph J. Nahas
发明人： Thomas W. Andre , Brad J. Garni , Joseph J. Nahas
IPC分类号： G11C5/14 , G11C7/10 , G11C7/06 , G11C7/02
CPC分类号： G11C7/02 , G11C7/062 , G11C11/1673
摘要： A memory circuit includes a sense amplifier in which a single reference signal is compared to two data signals from two memory cells. The reference signal is generated from the combination of memory cells in opposite logic states. The data signal capacitance is matched to the reference signal capacitance. With reduced but matched capacitance both high speed and high sensitivity can be achieved.
摘要翻译：存储器电路包括读出放大器，其中单个参考信号与来自两个存储器单元的两个数据信号进行比较。参考信号是以相反逻辑状态的存储单元的组合产生的。数据信号电容与参考信号电容匹配。通过降低但匹配的电容，可以实现高速度和高灵敏度。

26. 发明申请

US20070268741A1 Non-volatile memory cell and methods thereof 有权
标题翻译：非易失性存储单元及其方法
公开(公告)号：US20070268741A1
公开(公告)日：2007-11-22
申请号：US11438541
申请日：2006-05-22
申请人： Thomas W. Andre
发明人： Thomas W. Andre
IPC分类号： G11C11/00
CPC分类号： G11C11/15
摘要： A non-volatile storage element disposed at an integrated circuit is disclosed. The storage element includes a first resistive element having a first magnetic tunnel junction (MTJ) element, a first node coupled to the first resistive element, a second resistive element having of a second MTJ element, a second node coupled to the second resistive element, a sense amplifier having a first input coupled to the first node, a second input coupled to the second node, and an output, and a first conductor disposed to conduct a first current to set the first resistive element to a first resistive value and the second resistive element to a second resistive value different from the first resistive value.
摘要翻译：公开了一种设置在集成电路上的非易失性存储元件。存储元件包括具有第一磁性隧道结（MTJ）元件的第一电阻元件，耦合到第一电阻元件的第一节点，具有第二MTJ元件的第二电阻元件，耦合到第二电阻元件的第二节点，感测放大器，其具有耦合到第一节点的第一输入端，耦合到第二节点的第二输入端和输出端，以及布置成传导第一电流以将第一电阻元件设置为第一电阻值的第一导体，电阻元件到不同于第一电阻值的第二电阻值。

27. 发明授权

US07697321B2 Non-volatile memory cell and methods thereof 有权
标题翻译：非易失性存储单元及其方法
公开(公告)号：US07697321B2
公开(公告)日：2010-04-13
申请号：US11438541
申请日：2006-05-22
申请人： Thomas W. Andre
发明人： Thomas W. Andre
IPC分类号： G11C11/00
CPC分类号： G11C11/15
摘要： A non-volatile storage element disposed at an integrated circuit is disclosed. The storage element includes a first resistive element having a first magnetic tunnel junction (MTJ) element, a first node coupled to the first resistive element, a second resistive element having of a second MTJ element, a second node coupled to the second resistive element, a sense amplifier having a first input coupled to the first node, a second input coupled to the second node, and an output, and a first conductor disposed to conduct a first current to set the first resistive element to a first resistive value and the second resistive element to a second resistive value different from the first resistive value.
摘要翻译：公开了一种设置在集成电路上的非易失性存储元件。存储元件包括具有第一磁性隧道结（MTJ）元件的第一电阻元件，耦合到第一电阻元件的第一节点，具有第二MTJ元件的第二电阻元件，耦合到第二电阻元件的第二节点，感测放大器，其具有耦合到第一节点的第一输入端，耦合到第二节点的第二输入端和输出端，以及布置成传导第一电流以将第一电阻元件设置为第一电阻值的第一导体，电阻元件到不同于第一电阻值的第二电阻值。

28. 发明授权

US07747926B2 Methods and apparatus for a memory device with self-healing reference bits 有权
标题翻译：具有自修复参考位的存储器件的方法和装置
公开(公告)号：US07747926B2
公开(公告)日：2010-06-29
申请号：US11416850
申请日：2006-05-02
申请人： Loren J. Wise , Thomas W. Andre , Mark A. Durlam , Eric J. Salter
发明人： Loren J. Wise , Thomas W. Andre , Mark A. Durlam , Eric J. Salter
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G06F11/1008 , G11C11/16
摘要： A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the reference bits (104) is toggled to a different state if an error count is greater than a predetermined threshold. If the set of errors remains unchanged when subsequently read, the reference bit (104) is toggled back to its original state.
摘要翻译：诸如MRAM设备的存储器件包括与一组阵列位（102）相关联的自修复参考位（104）。存储器执行错误检测步骤（例如，使用纠错编码（ECC）算法）来检测数据位内的一组错误的存在，其中一个参考位（104）被切换到不同的状态，如果错误计数大于预定阈值，如果随后读取的错误集合保持不变，则将参考位（104）切换回其初始状态。

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