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21. 发明授权

US06864701B2 Test patterns for measurement of effective vacancy diffusion area 失效
标题翻译：用于测量有效空位扩散面积的测试模式
公开(公告)号：US06864701B2
公开(公告)日：2005-03-08
申请号：US10602147
申请日：2003-06-24
申请人： Chih-Hsiang Yao , Tai-Chun Huang
发明人： Chih-Hsiang Yao , Tai-Chun Huang
IPC分类号： H01L23/544 , G01R31/26
CPC分类号： H01L22/34
摘要： A test pattern (100, 200, 300, 400, 600, 700) has a first metal structure (102) disposed on a substrate (352), one or more intermediate layers (358) disposed above the first metal structure (102) and a second metal structure (104) disposed above the one or more intermediate layers (352). A first via (106) passes through the intermediate layers (352) and connects the first metal structure (102) to the second metal structure (104). One or more third metal structures (108) are disposed above the one or more intermediate layers (352) and the first metal structure (102). One or more second vias (110) pass through the intermediate layers (352) and connect the first metal structure (102) to the third metal structures (108). The second vias (110) are located outside of a radius (R) from a center of the first via (106). The third metal structures (110) are separated from the second metal structure (104) by a dielectric material (366).
摘要翻译：测试图案（100,200,300,400,600,700）具有设置在基底（352）上的第一金属结构（102），设置在第一金属结构（102）上方的一个或多个中间层（358）和设置在所述一个或多个中间层（352）上方的第二金属结构（104）。第一通孔（106）穿过中间层（352）并将第一金属结构（102）连接到第二金属结构（104）。一个或多个第三金属结构（108）设置在一个或多个中间层（352）和第一金属结构（102）上方。一个或多个第二通孔（110）穿过中间层（352）并将第一金属结构（102）连接到第三金属结构（108）。第二通路（110）位于距离第一通孔（106）的中心的半径（R）的外侧。第三金属结构（110）通过介电材料（366）与第二金属结构（104）分离。

22. 发明申请

US20050006782A1 TEST PATTERNS FOR MEASUREMENT OF EFFECTIVE VACANCY DIFFUSION AREA 失效
标题翻译：用于测量有效的VACANCY扩张区的测试模式
公开(公告)号：US20050006782A1
公开(公告)日：2005-01-13
申请号：US10602147
申请日：2003-06-24
申请人： Chih-Hsiang Yao , Tai-Chun Huang
发明人： Chih-Hsiang Yao , Tai-Chun Huang
IPC分类号： H01L23/544 , H01L21/66
CPC分类号： H01L22/34
摘要： A test pattern (100, 200, 300, 400, 600, 700) has a first metal structure (102) disposed on a substrate (352), one or more intermediate layers (358) disposed above the first metal structure (102) and a second metal structure (104) disposed above the one or more intermediate layers (352). A first via (106) passes through the intermediate layers (352) and connects the first metal structure (102) to the second metal structure (104). One or more third metal structures (108) are disposed above the one or more intermediate layers (352) and the first metal structure (102). One or more second vias (110) pass through the intermediate layers (352) and connect the first metal structure (102) to the third metal structures (108). The second vias (110) are located outside of a radius (R) from a center of the first via (106). The third metal structures (110) are separated from the second metal structure (104) by a dielectric material (366).
摘要翻译：测试图案（100,200,300,400,600,700）具有设置在基底（352）上的第一金属结构（102），设置在第一金属结构（102）上方的一个或多个中间层（358）和设置在所述一个或多个中间层（352）上方的第二金属结构（104）。第一通孔（106）穿过中间层（352）并将第一金属结构（102）连接到第二金属结构（104）。一个或多个第三金属结构（108）设置在一个或多个中间层（352）和第一金属结构（102）上方。一个或多个第二通孔（110）穿过中间层（352）并将第一金属结构（102）连接到第三金属结构（108）。第二通路（110）位于距离第一通孔（106）的中心的半径（R）的外侧。第三金属结构（110）通过介电材料（366）与第二金属结构（104）分离。

23. 发明授权

US08435802B2 Conductor layout technique to reduce stress-induced void formations 有权
标题翻译：导体布置技术，以减少应力引起的空隙形成
公开(公告)号：US08435802B2
公开(公告)日：2013-05-07
申请号：US11438127
申请日：2006-05-22
申请人： Min-Hwa Chi , Tai-Chun Huang , Chih-Hsiang Yao
发明人： Min-Hwa Chi , Tai-Chun Huang , Chih-Hsiang Yao
IPC分类号： H01L21/00
CPC分类号： H01L21/76898 , H01L21/768 , H01L23/528 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.
摘要翻译：通过退火工艺制备半导体器件，通过由绝缘体材料包围的导体线来互连器件的至少两个部件。退火过程导致在导线和绝缘体材料内形成残余应力。在掩模的选择性部分上的布局中设计凹口，用于图案化导体线。选择部分上的凹口形状的存在在不存在凹口的情况下，在导线内产生额外的应力分量。选择凹口的位置使得额外的应力分量基本上抵消残余应力，从而导致残余应力的净减小。残余应力的减小导致相应的机械应力迁移，从而提高了装置的可靠性。

24. 发明授权

US07772701B2 Integrated circuit having improved interconnect structure 有权
标题翻译：具有改进的互连结构的集成电路
公开(公告)号：US07772701B2
公开(公告)日：2010-08-10
申请号：US11422769
申请日：2006-06-07
申请人： Chih-Hsiang Yao , Tai-Chun Huang , Mong-Song Liang
发明人： Chih-Hsiang Yao , Tai-Chun Huang , Mong-Song Liang
IPC分类号： H01L23/48 , H01L29/40
CPC分类号： H01L23/522 , H01L23/481 , H01L23/53228 , H01L23/5329 , H01L23/53295 , H01L2224/0401 , H01L2224/0557 , H01L2224/13023 , H01L2224/131 , H01L2924/0002 , H01L2924/13091 , H01L2924/00014 , H01L2224/05552 , H01L2924/00
摘要： An improved integrated circuit structure and method of making the same is provided. The integrated circuit structure comprises a substrate, the substrate having a top surface and a bottom surface. The top surface has a circuit device formed thereon. The structure includes a plurality of metallization layers, a bonding structure formed over the bottom surface and a conductive interconnect structure formed through said substrate.
摘要翻译：提供了一种改进的集成电路结构及其制造方法。集成电路结构包括基板，该基板具有顶表面和底表面。顶表面上形成有电路装置。该结构包括多个金属化层，形成在底表面上的接合结构和通过所述衬底形成的导电互连结构。

25. 发明授权

US06927498B2 Bond pad for flip chip package 有权
公开(公告)号：US06927498B2
公开(公告)日：2005-08-09
申请号：US10716682
申请日：2003-11-19
申请人： Tai-Chun Huang , Chih-Hsiang Yao , Ching-Hua Hsieh
发明人： Tai-Chun Huang , Chih-Hsiang Yao , Ching-Hua Hsieh
IPC分类号： H01L23/485 , H01L23/29
CPC分类号： H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/0401 , H01L2224/05093 , H01L2224/13099 , H01L2224/45124 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/351 , H01L2924/00 , H01L2224/48
摘要： A bond pad for a flip chip package. The bond pad is suitable for an integrated circuit chip. A plurality of slots are designed in the bond pad. Each of the slots extends along a direction which is perpendicular to a radial direction from the center of the bond pad. The bond pad is deposed at the corner of the integrated circuit chip.

26. 发明申请

US20050133241A1 Chip orientation and attachment method 审中-公开
标题翻译：芯片方向和贴装方法
公开(公告)号：US20050133241A1
公开(公告)日：2005-06-23
申请号：US10742240
申请日：2003-12-18
申请人： Kuan-Shou Chi , Tai-Chun Huang , Chih-Hsiang Yao
发明人： Kuan-Shou Chi , Tai-Chun Huang , Chih-Hsiang Yao
IPC分类号： H01L21/58 , H01L21/60 , H01L23/02 , H05K3/30
CPC分类号： H01L24/83 , H01L24/29 , H01L2224/2919 , H01L2224/45124 , H01L2224/83121 , H01L2224/83191 , H01L2224/83801 , H01L2224/8385 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/351 , Y10T29/4913 , Y10T29/49133 , H01L2924/00 , H01L2224/48
摘要： A chip orientation and attachment method is disclosed which eliminates or substantially reduces chip damage caused by thermal stress induced by application of a molding compound to the chip and substrate. The chip is attached to the substrate in such a manner that at least one of the following conditions exists: the chip diagonal and the substrate diagonal are in non-aligned relationship, and/or the chip edges are non-parallel with respect to the substrate edges, and/or the chip center is in non-overlapping relationship with respect to the substrate center. The invention includes chip package structures fabricated according to the chip orientation and attachment method.
摘要翻译：公开了一种芯片取向和附接方法，其消除或基本上减少由于将模塑料施加到芯片和基板而引起的热应力引起的芯片损伤。芯片以这样的方式附接到基板，使得存在以下条件中的至少一个：芯片对角线和基板对角线处于非对准关系，和/或芯片边缘相对于基板不平行边缘和/或芯片中心相对于基板中心处于非重叠关系。本发明包括根据芯片取向和附着方法制造的芯片封装结构。

27. 发明申请

US20050127529A1 Structure and method for reinforcing a bond pad on a chip 有权
标题翻译：用于加强芯片上的接合焊盘的结构和方法
公开(公告)号：US20050127529A1
公开(公告)日：2005-06-16
申请号：US10731983
申请日：2003-12-10
申请人： Tai-Chun Huang , Chih-Hsiang Yao
发明人： Tai-Chun Huang , Chih-Hsiang Yao
IPC分类号： H01L21/44 , H01L23/48 , H01L23/485 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L24/03 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05624 , H01L2224/05647 , H01L2224/131 , H01L2224/48463 , H01L2224/85207 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： A structure for reinforcing or anchoring a bond pad on a chip. The structure includes a bonding pad provided in a dielectric layer, at least one conductive layer provided beneath and in electrical contact with the bonding pad, and at least one parallel-interconnect anchor structure provided in contact with the bonding pad and the conductive layer. The anchor structure or structures prevent the bonding pad from exerting excessive force against the dielectric layer and cracking the dielectric layer when the chip is subjected to physical testing. The bonding pad may have truncated or curved corners, for example.
摘要翻译：用于加强或固定芯片上的焊盘的结构。该结构包括设置在电介质层中的接合焊盘，设置在接合焊盘下方并与接合焊盘电接触的至少一个导电层以及与接合焊盘和导电层接触地设置的至少一个平行互连锚固结构。锚定结构或结构防止接合垫在芯片进行物理测试时对电介质层施加过大的力并破坏电介质层。例如，接合焊盘可以具有截头或弯曲的拐角。

28. 发明授权

US07741714B2 Bond pad structure with stress-buffering layer capping interconnection metal layer 有权
标题翻译：具有应力缓冲层封接互连金属层的焊盘结构
公开(公告)号：US07741714B2
公开(公告)日：2010-06-22
申请号：US10979408
申请日：2004-11-02
申请人： Tai-Chun Huang , Chih-Hsiang Yao , Wen-Kai Wan
发明人： Tai-Chun Huang , Chih-Hsiang Yao , Wen-Kai Wan
IPC分类号： H01L23/52
CPC分类号： H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02125 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/05076 , H01L2224/05083 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05147 , H01L2224/05157 , H01L2224/05166 , H01L2224/05171 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05576 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48624 , H01L2224/48724 , H01L2224/48799 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/0496 , H01L2924/05042 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2924/01004 , H01L2924/01077 , H01L2224/48824 , H01L2924/00 , H01L2924/00012
摘要： A bond pad structure for an integrated circuit chip has a stress-buffering layer between a top interconnection level metal layer and a bond pad layer to prevent damages to the bond pad structure from wafer probing and packaging impacts. The stress-buffering layer is a conductive material having a property selected from the group consisting of Young's modulus, hardness, strength and toughness greater than the top interconnection level metal layer or the bond pad layer. For improving adhesion and bonding strength, the lower portion of the stress-buffering layer may be modified as various forms of a ring, a mesh or interlocking-grid structures embedded in a passivation layer, alternatively, the stress-buffering layer may has openings filled with the bond pad layer.
摘要翻译：用于集成电路芯片的接合焊盘结构在顶部互连级金属层和接合焊盘层之间具有应力缓冲层，以防止焊盘结构对晶片探测和封装冲击的损害。应力缓冲层是具有选自杨氏模量，硬度，强度和韧性大于顶部互连级金属层或接合焊盘层的性质的导电材料。为了提高附着力和粘结强度，应力缓冲层的下部可以被修改为嵌入钝化层中的各种形式的环，网或互锁网格结构，或者应力缓冲层可以具有开口与焊垫层。

29. 发明授权

US07074629B2 Test patterns for measurement of effective vacancy diffusion area 失效
标题翻译：用于测量有效空位扩散面积的测试模式
公开(公告)号：US07074629B2
公开(公告)日：2006-07-11
申请号：US11018604
申请日：2004-12-21
申请人： Chih-Hsiang Yao , Tai-Chun Huang
发明人： Chih-Hsiang Yao , Tai-Chun Huang
IPC分类号： G01R31/26
CPC分类号： H01L22/34
摘要： A test pattern (100, 200, 300, 400, 600, 700) has a first metal structure (102) disposed on a substrate (352), one or more intermediate layers (358) disposed above the first metal structure (102) and a second metal structure (104) disposed above the one or more intermediate layers (352). A first via (106) passes through the intermediate layers (352) and connects the first metal structure (102) to the second metal structure (104). One or more third metal structures (108) are disposed above the one or more intermediate layers (352) and the first metal structure (102). One or more second vias (110) pass through the intermediate layers (352) and connect the first metal structure (102) to the third metal structures (108). The second vias (110) are located outside of a radius (R) from a center of the first via (106). The third metal structures (110) are separated from the second metal structure (104) by a dielectric material (366).
摘要翻译：测试图案（100,200,300,400,600,700）具有设置在基底（352）上的第一金属结构（102），设置在第一金属结构（102）上方的一个或多个中间层（358）和设置在所述一个或多个中间层（352）上方的第二金属结构（104）。第一通孔（106）穿过中间层（352）并将第一金属结构（102）连接到第二金属结构（104）。一个或多个第三金属结构（108）设置在一个或多个中间层（352）和第一金属结构（102）上方。一个或多个第二通孔（110）穿过中间层（352）并将第一金属结构（102）连接到第三金属结构（108）。第二通路（110）位于距离第一通孔（106）的中心的半径（R）的外侧。第三金属结构（110）通过介电材料（366）与第二金属结构（104）分离。

30. 发明申请

US20050158967A1 Semiconductor chip singulation method 有权
标题翻译：半导体芯片单片化方法
公开(公告)号：US20050158967A1
公开(公告)日：2005-07-21
申请号：US10761004
申请日：2004-01-20
申请人： Tai-Chun Huang , Kuan-Shou Chi , Chih-Hsiang Yao
发明人： Tai-Chun Huang , Kuan-Shou Chi , Chih-Hsiang Yao
IPC分类号： H01L21/301 , H01L21/46 , H01L21/78
CPC分类号： H01L21/78 , Y10S438/907
摘要： A method to singulate a circuit die from an integrated circuit wafer is achieved. The method comprises providing an integrated circuit wafer containing a circuit die. The integrated circuit wafer is cut through by performing a single, continuous cut around the perimeter of the circuit die to thereby singulate the circuit die.
摘要翻译：实现了从集成电路晶片中分离电路管芯的方法。该方法包括提供包含电路管芯的集成电路晶片。通过围绕电路管芯的周边执行单个连续的切割来切割集成电路晶片，从而对电路管芯进行分离。

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