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21. 发明申请

US20050110148A1 FUSE STUCTURE 有权
标题翻译：保险丝座
公开(公告)号：US20050110148A1
公开(公告)日：2005-05-26
申请号：US10904081
申请日：2004-10-22
申请人： Chiu-Te Lee , Te-Yuan Wu
发明人： Chiu-Te Lee , Te-Yuan Wu
IPC分类号： H01L21/60 , H01L23/525 , H01L29/40
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A metal layer structure is disclosed. The metal layer structure includes a substrate, a first dielectric layer on a surface of the substrate, and at least one first conductor and at least one second conductor on the first dielectric layer. The second conductor has at least one thin portion.
摘要翻译：公开了一种金属层结构。金属层结构包括基板，在基板的表面上的第一介电层以及第一介电层上的至少一个第一导体和至少一个第二导体。第二导体具有至少一个薄部分。

22. 发明授权

US06864124B2 Method of forming a fuse 有权
标题翻译：形成保险丝的方法
公开(公告)号：US06864124B2
公开(公告)日：2005-03-08
申请号：US10064052
申请日：2002-06-05
申请人： Chiu-Te Lee , Te-Yuan Wu
发明人： Chiu-Te Lee , Te-Yuan Wu
IPC分类号： H01L21/60 , H01L23/525 , H01L21/82
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A surface of a semiconductor substrate defined with at least one fuse area and at least one bonding pad area. A conductive layer with a thickness of 12 kÅ and a protective layer are sequentially formed on the surface of the semiconductor substrate. Then portions of the protective layer and portions of the conductive layer in the fuse area are etched to make the thickness for the remaining conductive layer in the fuse area be approximately 5 kÅ. Finally a dielectric layer is formed on the surface of the semiconductor substrate, and portions of the first dielectric layer and portions of the protective layer in the bonding pad area are etched until reaching the top surface of the conductive layer.
摘要翻译：半导体衬底的表面，其被限定有至少一个熔丝区域和至少一个焊盘区域。在半导体衬底的表面上依次形成厚度为12kA的导电层和保护层。然后，将保护层的部分和熔丝区域中的导电层的部分进行蚀刻，以使保险丝区域中的剩余导电层的厚度为约5k。最后，在半导体衬底的表面上形成电介质层，并且蚀刻第一电介质层的部分和焊盘区域中的保护层的部分，直到到达导电层的顶表面。

23. 发明申请

US20120038414A1 METHOD FOR OPERATING SEMICONDUCTOR DEVICE 有权
标题翻译：操作半导体器件的方法
公开(公告)号：US20120038414A1
公开(公告)日：2012-02-16
申请号：US13282482
申请日：2011-10-27
申请人： Sung-Nien Tang , Wei-Lun Hsu , Ching-Ming Lee , Te-Yuan Wu
发明人： Sung-Nien Tang , Wei-Lun Hsu , Ching-Ming Lee , Te-Yuan Wu
IPC分类号： G05F3/02
CPC分类号： H01L27/085 , H01L29/7817 , H03F3/195
摘要： A method for operating a semiconductor device including a lateral double diffused metal oxide semiconductor (LDMOS) with a first source, a common drain and a first gate, a junction field effect transistor (JFET) with a second source, the common drain and a second gate wherein the second source is electrically connected to the first gate and an inner circuit electrically connected to the first source is provided. The first source provides the inner circuit with an inner current to generate an inner voltage by means of the lateral double diffused metal oxide semiconductor, and the lateral double diffused metal oxide semiconductor turns off when the inner voltage is elevated substantially as high as the first gate voltage.
摘要翻译：一种用于操作包括具有第一源极，公共漏极和第一栅极的横向双扩散金属氧化物半导体（LDMOS）的半导体器件的方法，具有第二源极的结型场效应晶体管（JFET），所述公共漏极和第二源极栅极，其中第二源极电连接到第一栅极，并且提供与第一源电连接的内部电路。第一源为内部电路提供内部电流，以通过横向双扩散金属氧化物半导体产生内部电压，并且当内部电压升高到与第一栅极高相同时，横向双扩散金属氧化物半导体截止电压。

24. 发明授权

US08072011B2 Semiconductor device and method for operating the same 有权
标题翻译：半导体装置及其操作方法
公开(公告)号：US08072011B2
公开(公告)日：2011-12-06
申请号：US12573884
申请日：2009-10-06
申请人： Sung-Nien Tang , Wei-Lun Hsu , Ching-Ming Lee , Te-Yuan Wu
发明人： Sung-Nien Tang , Wei-Lun Hsu , Ching-Ming Lee , Te-Yuan Wu
IPC分类号： H01L29/80 , H01L31/112
CPC分类号： H01L27/085 , H01L29/7817 , H03F3/195
摘要： A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first gate. The junction field effect transistor includes a second source, the common drain and a second gate. The second source is electrically connected to the first gate. The inner circuit is electrically connected to the first source.
摘要翻译：半导体器件包括横向双扩散金属氧化物半导体（LDMOS），结型场效应晶体管（JFET）和内部电路。横向双扩散金属氧化物半导体包括第一源极，公共漏极和第一栅极。结型场效应晶体管包括第二源极，公共漏极和第二栅极。第二源电连接到第一栅极。内部电路电连接到第一源。

25. 发明授权

US08179188B2 Method for operating semiconductor device 有权
标题翻译：半导体器件的操作方法
公开(公告)号：US08179188B2
公开(公告)日：2012-05-15
申请号：US13282482
申请日：2011-10-27
申请人： Sung-Nien Tang , Wei-Lun Hsu , Ching-Ming Lee , Te-Yuan Wu
发明人： Sung-Nien Tang , Wei-Lun Hsu , Ching-Ming Lee , Te-Yuan Wu
IPC分类号： H03K17/687
CPC分类号： H01L27/085 , H01L29/7817 , H03F3/195
摘要： A method for operating a semiconductor device including a lateral double diffused metal oxide semiconductor (LDMOS) with a first source, a common drain and a first gate, a junction field effect transistor (JFET) with a second source, the common drain and a second gate wherein the second source is electrically connected to the first gate and an inner circuit electrically connected to the first source is provided. The first source provides the inner circuit with an inner current to generate an inner voltage by means of the lateral double diffused metal oxide semiconductor, and the lateral double diffused metal oxide semiconductor turns off when the inner voltage is elevated substantially as high as the first gate voltage.
摘要翻译：一种用于操作包括具有第一源极，公共漏极和第一栅极的横向双扩散金属氧化物半导体（LDMOS）的半导体器件的方法，具有第二源极的结型场效应晶体管（JFET），所述公共漏极和第二源极栅极，其中第二源极电连接到第一栅极，并且提供与第一源电连接的内部电路。第一源为内部电路提供内部电流，以通过横向双扩散金属氧化物半导体产生内部电压，并且当内部电压升高到与第一栅极高相同时，横向双扩散金属氧化物半导体截止电压。

26. 发明申请

US20110080213A1 SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME 有权
标题翻译：半导体器件及其操作方法
公开(公告)号：US20110080213A1
公开(公告)日：2011-04-07
申请号：US12573884
申请日：2009-10-06
申请人： Sung-Nien Tang , Wei-Lun Hsu , Ching-Ming Lee , Te-Yuan Wu
发明人： Sung-Nien Tang , Wei-Lun Hsu , Ching-Ming Lee , Te-Yuan Wu
IPC分类号： H03K3/353 , H01L27/088
CPC分类号： H01L27/085 , H01L29/7817 , H03F3/195
摘要： A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first gate. The junction field effect transistor includes a second source, the common drain and a second gate. The second source is electrically connected to the first gate. The inner circuit is electrically connected to the first source.
摘要翻译：半导体器件包括横向双扩散金属氧化物半导体（LDMOS），结型场效应晶体管（JFET）和内部电路。横向双扩散金属氧化物半导体包括第一源极，公共漏极和第一栅极。结型场效应晶体管包括第二源极，公共漏极和第二栅极。第二源电连接到第一栅极。内部电路电连接到第一源。

27. 发明授权

US07301216B2 Fuse structure 有权
标题翻译：保险丝结构
公开(公告)号：US07301216B2
公开(公告)日：2007-11-27
申请号：US10711790
申请日：2004-10-05
申请人： Chiu-Te Lee , Te-Yuan Wu
发明人： Chiu-Te Lee , Te-Yuan Wu
IPC分类号： H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A metal layer structure is disclosed. The metal layer structure includes a substrate, a first dielectric layer on a surface of the substrate, and at least one first conductor and at least one second conductor on the first dielectric layer. The second conductor has at least one thin portion.
摘要翻译：公开了一种金属层结构。金属层结构包括基板，在基板的表面上的第一介电层以及第一介电层上的至少一个第一导体和至少一个第二导体。第二导体具有至少一个薄部分。

28. 发明授权

US06251725B1 Method of fabricating a DRAM storage node on a semiconductor wafer 失效
标题翻译：在半导体晶片上制造DRAM存储节点的方法
公开(公告)号：US06251725B1
公开(公告)日：2001-06-26
申请号：US09479934
申请日：2000-01-10
申请人： Jung-Chao Chiou , Te-Yuan Wu , Chuan-Fu Wang
发明人： Jung-Chao Chiou , Te-Yuan Wu , Chuan-Fu Wang
IPC分类号： H01L218242
CPC分类号： H01L21/76831 , H01L21/76816 , H01L27/10855 , H01L28/60 , H01L28/84
摘要： A semiconductor wafer comprises a substrate, a first conductive layer and a dielectric layer covering the first conductive layer. A thin-film layer is formed over the dielectric layer. The thin-film layer comprises a hole that penetrates down to the surface of the dielectric layer and the hole is located above the first conductive layer. A first barrier layer is formed on the surface of the semiconductor wafer to cover the thin-film layer. Next, a spacer is formed on the internal walls of the hole. Thereafter, a first dry etching process is performed to form a contact hole. A second barrier layer is then formed on the internal walls of the contact hole. A second conductive layer is formed on the surface of the semiconductor wafer that fills the contact hole. A lithographic process is performed to define a pattern and a location of the storage node in a photo resist layer above the contact hole. A second dry etching process is used to etch the second conductive layer using the photo resist layer as a mask so as to form the storage node. Finally, the photo resist layer is removed.
摘要翻译：半导体晶片包括衬底，第一导电层和覆盖第一导电层的电介质层。在电介质层上形成薄膜层。薄膜层包括穿透到介电层的表面的孔，并且孔位于第一导电层的上方。在半导体晶片的表面上形成第一阻挡层以覆盖薄膜层。接下来，在孔的内壁上形成间隔物。此后，进行第一干蚀刻工艺以形成接触孔。然后在接触孔的内壁上形成第二阻挡层。在填充接触孔的半导体晶片的表面上形成第二导电层。执行光刻处理以限定存储节点在接触孔上方的光致抗蚀剂层中的图案和位置。使用第二干法蚀刻工艺来蚀刻使用光致抗蚀剂层作为掩模的第二导电层，以形成存储节点。最后，除去光刻胶层。

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