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22. 发明授权

US06787408B2 Method for forming an electrical insulating layer on bit lines of the flash memory 有权
标题翻译：在闪速存储器的位线上形成电绝缘层的方法
公开(公告)号：US06787408B2
公开(公告)日：2004-09-07
申请号：US09930856
申请日：2001-08-16
申请人： Chien-Wei Chen , Jiun-Ren Lai
发明人： Chien-Wei Chen , Jiun-Ren Lai
IPC分类号： H01L21338
CPC分类号： H01L27/11517 , H01L21/31055 , H01L27/115
摘要： A method for forming an electrical insulating layer on bit lines of the flash memory is disclosed. A conductive layer, a mask layer and a cap layer are sequentially formed on a semiconductor substrate and then are etched to form a plurality of spacing. Afterwards, a dielectric layer is formed on the semiconductor substrate and a planarized layer is then formed on the dielectric layer. The planarized layer and the dielectric layer are etched sequentially wherein the etching rate of the planarized layer is less than that of the dielectric layer. Next, the dielectric layer is etched to remove a portion of the dielectric layer wherein the etching rate of the dielectric layer is higher than that of the cap layer, and thus a spacing dielectric layer is formed on the spacing. Thereafter, the cap layer is stripped wherein the etching rate of the dielectric layer is less than that of the mask layer so that the spacing dielectric layer has a round top and slant sides. Finally, the mask layer is stripped and then the spacing dielectric layer remains to form the electrical insulating layer on bit lines of the flash memory.
摘要翻译：公开了一种在闪速存储器的位线上形成电绝缘层的方法。依次在半导体衬底上形成导电层，掩模层和覆盖层，然后进行蚀刻以形成多个间隔。之后，在半导体衬底上形成电介质层，然后在电介质层上形成平坦化层。依次蚀刻平坦化层和电介质层，其中平坦化层的蚀刻速率小于电介质层的蚀刻速率。接下来，蚀刻电介质层以去除电介质层的一部分，其中电介质层的蚀刻速率高于盖层的蚀刻速率，因此在间隔上形成间隔电介质层。此后，剥离盖层，其中电介质层的蚀刻速率小于掩模层的蚀刻速率，使得间隔电介质层具有圆顶和倾斜的侧面。最后，剥离掩模层，然后保留间隔电介质层以在闪存的位线上形成电绝缘层。

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