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21. 发明授权

US4818901A Controlled switching CMOS output buffer 失效
标题翻译：控制开关CMOS输出缓冲器
公开(公告)号：US4818901A
公开(公告)日：1989-04-04
申请号：US75641
申请日：1987-07-20
申请人： William R. Young , Harold D. Davidson
发明人： William R. Young , Harold D. Davidson
IPC分类号： H03K19/00 , H03K19/003 , H03K19/017 , H03K19/094 , H03K17/13
CPC分类号： H03K19/00315 , H03K19/0013 , H03K19/01721 , H03K19/09429
摘要： An output buffer initially operating its output transistors in a constant current mode in response to an input signal transition and subsequently operating its output transistors in a constant voltage drive mode as the output approaches the desried output level. The control electrode of the output transistor is controlled by a switchable voltage divider or current mirror. The control of an output transistor may not be activated until the other output transistor is turned off to prevent having both output devices on at the same time.
摘要翻译：输出缓冲器首先响应于输入信号转换以恒定电流模式操作其输出晶体管，并随后在输出接近输出电平时以恒定电压驱动模式操作其输出晶体管。输出晶体管的控制电极由可切换的分压器或电流镜控制。输出晶体管的控制可能不会被激活，直到另一个输出晶体管截止，以防止同时打开两个输出器件。

22. 发明授权

US4264874A Low voltage CMOS amplifier 失效
标题翻译：低电压CMOS放大器
公开(公告)号：US4264874A
公开(公告)日：1981-04-28
申请号：US872281
申请日：1978-01-25
申请人： William R. Young
发明人： William R. Young
IPC分类号： H03F1/30 , H03F3/16
CPC分类号： H03F1/301
摘要： A CMOS amplifier having a pair of CMOS load and amplifying devices connected in series, two parallel pairs of CMOS devices with interconnected gates to form current mirrors and connected to the gate of the load MOS device to compensate the gain for variations in power supply voltage, temperature and transistor parameters, a feedback MOS device having its source-drain path connected between the junction of the load and amplifying MOS and the gate of the amplifying MOS to provide nonlinear, negative feedback, and a resistor connected in parallel with the feedback MOS device to establish an initial self-biasing voltage level for the amplifying MOS below the threshold voltage of the feedback MOS.
摘要翻译：具有串联连接的一对CMOS负载和放大装置的CMOS放大器，具有互连栅极的两个并联的CMOS器件对以形成电流镜并连接到负载MOS器件的栅极，以补偿电源电压变化的增益，温度和晶体管参数，其源极 - 漏极路径连接在负载和放大MOS的结点与放大MOS的栅极之间以提供非线性负反馈的反馈MOS器件和与反馈MOS器件并联连接的电阻器以建立低于反馈MOS的阈值电压的放大MOS的初始自偏置电压电平。

23. 发明授权

US4249963A Method for improving a property of an alloy 失效
标题翻译：提高合金性能的方法
公开(公告)号：US4249963A
公开(公告)日：1981-02-10
申请号：US59796
申请日：1979-07-23
申请人： William R. Young
发明人： William R. Young
IPC分类号： C22C1/00 , B23K35/30 , C21D3/00 , C22C3/00 , C23F1/12 , C21D1/74 , C22F1/02
CPC分类号： B23K35/38 , B23K35/30 , C21D3/00 , C23F1/12
摘要： A property, such as ductility, mechanical strength and increased remelt temperature, of an alloy, for example one which includes an element such as Si or B, or both, is improved by depletion of such an element through the alloy surface. This is accomplished by exposing the alloy surface, one common form of which is a brazing alloy, to gaseous ions such as fluoride ions, while heating the alloy at a temperature which is not detrimental to the alloy or members associated with the alloy. Heating is conducted for a time sufficient for such elements, for example those selected from Si and B, included as a melting point depressant, to diffuse to the surface of the alloy and to react with the gaseous ions to form a gaseous compound of the element. Such gaseous compound then separates from the surface, thereby depleting the alloy of the element and improving at least one property.
摘要翻译：通过合金表面的这种元素的消耗，可以改善合金例如包括诸如Si或B的元素或两者的合金的延展性，机械强度和增加的熔融温度的性质。这是通过将合金表面（其一种常见形式是钎焊合金）暴露于诸如氟离子的气态离子而实现的，同时在对合金或与合金相关的构件不利的温度下加热合金。进行加热进行足够的时间，这些元素例如包括作为熔点降低剂的Si和B元素扩散到合金表面并与气态离子反应以形成元素的气态化合物。这样的气体化合物然后与表面分离，从而消耗元素的合金并改善至少一种性质。

24. 发明授权

US07064363B2 Symmetric inducting device for an integrated circuit having a ground shield 有权
公开(公告)号：US07064363B2
公开(公告)日：2006-06-20
申请号：US10855948
申请日：2004-05-28
申请人： Rex Everett Lowther , William R. Young
发明人： Rex Everett Lowther , William R. Young
IPC分类号： H01L29/80 , H01L31/112
CPC分类号： H01L28/10 , H01F17/0013 , H01F27/367 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to integrated circuits having symmetric inducting devices with a ground shield. In one embodiment, a symmetric inducting device for an integrated circuit comprises a substrate, a main metal layer and a shield. The substrate has a working surface. The main metal layer has at least one pair of current path regions. Each of the current path region pairs is formed in generally a regular polygonal shape that is generally symmetric about a plane of symmetry that is perpendicular to the working surface of the substrate. The shield is patterned into segments that are generally symmetric about the plane of symmetry. Medial portions of at least some segments of the shield are formed generally perpendicular to the plane of symmetry as the medial portions cross the plane of symmetry.

25. 发明授权

US06522117B1 Reference current/voltage generator having reduced sensitivity to variations in power supply voltage and temperature 失效
标题翻译：参考电流/电压发生器对电源电压和温度的变化具有降低的灵敏度
公开(公告)号：US06522117B1
公开(公告)日：2003-02-18
申请号：US09880726
申请日：2001-06-13
申请人： William R. Young , Gregg D. Croft
发明人： William R. Young , Gregg D. Croft
IPC分类号： G05F316
CPC分类号： G05F3/267 , Y10S323/907
摘要： A reference current/voltage gnereator is insensitive to variations in power supply voltage and temperature. The operational parameters of matched current mirror transistors of the generator are effectively equalized by an auxiliary bias amplifier, whose transistors are matched with and connected to the current mirror transistors of the generator in such a manner as to maintain the same electrical parameters in each of the current mirror legs of the current generator, irrespective of variations in supply voltage. Temperature insensitivity is achieved by making the output current mirror a current that is the sum of two currents whose current paths complementary temperature coefficients.
摘要翻译：参考电流/电压发生器对电源电压和温度的变化不敏感。发电机的匹配电流镜晶体管的工作参数通过辅助偏置放大器有效地相等，其辅助偏置放大器的晶体管与发生器的电流镜像晶体管相匹配并连接到发生器的电流镜像晶体管，电流发生器的电流镜腿，与电源电压的变化无关。通过使输出电流镜为电流为互补温度系数的两个电流的和的电流来实现温度不敏感。

26. 发明授权

US06492705B1 Integrated circuit air bridge structures and methods of fabricating same 失效
标题翻译：集成电路空气桥结构及其制造方法
公开(公告)号：US06492705B1
公开(公告)日：2002-12-10
申请号：US08658010
申请日：1996-06-04
申请人： Patrick A. Begley , William R. Young , Anthony L. Rivoli , Jose Avelino Delgado , Stephen J. Gaul
发明人： Patrick A. Begley , William R. Young , Anthony L. Rivoli , Jose Avelino Delgado , Stephen J. Gaul
IPC分类号： H01L2900
CPC分类号： H01L28/10 , H01L21/7682 , H01L23/5221 , H01L2924/0002 , H01L2924/00
摘要： Airbridge structures and processes for making air bridge structures and integrated circuits are disclosed. One airbridge structure has metal conductors 24 encased in a sheath of dielectric material 249. The conductors extend across a cavity 244 and a semiconductor substrate 238. In one embodiment, the conductors traversing the cavity 244 are supported by posts 248 that extend from the substrate. In another embodiment, oxide posts 258 extend from the substrate to support the conductors. In another embodiment, trenches 101 are made in a device substrate 110 bonded to a handle substrate 100. The trenches are filled with a dielectric and a conductor pattern is formed over the filled trenches. The substrate material between the conductors is then removed to leave a pattern of posts 116, 114, 112 that included dielectrically encased conductors 106. In another bonded wafer embodiment, conductors 204 are encased in a dielectric above a sacrificial device region. The device region is isolated by suitably filled trenches. Vias 224, 226 in the dielectric 205 allow removal of the substrate material to form a cavity 208 beneath the conductors 204. Other embodiments included a conductor 42 encased in dielectric that is formed above a region from which sacrificial polysilicon is removed to form a cavity 66. It is still another embodiment the conductor 42 is enclosed in a dielectric above a cavity 66a from which device material is removed.
摘要翻译：公开了用于制造空气桥结构和集成电路的空中桥梁结构和工艺。一个空中桥结构具有包裹在电介质材料249的护套中的金属导体24.导体延伸穿过空腔244和半导体衬底238.在一个实施例中，穿过空腔244的导体由从衬底延伸的柱248支撑。在另一个实施例中，氧化物柱258从衬底延伸以支撑导体。在另一个实施例中，沟槽101被制成接合到手柄衬底100的器件衬底110.沟槽填充有电介质，并且导体图案形成在填充的沟槽。然后去除导体之间的衬底材料以留下包括介电封装的导体106的柱116,114,112的图案。在另一个接合晶片实施例中，导体204被封装在牺牲器件区域之上的电介质中。器件区域由适当填充的沟槽隔离。电介质205中的通孔224,226允许去除衬底材料以在导体204下方形成空腔208.其它实施例包括封装在电介质中的导体42，导电体42形成在除去牺牲多晶硅以形成空腔66的区域之上还有另一个实施例，导体42封闭在空腔66a之上的电介质中，器件材料从该空腔中被去除。

27. 发明授权

US06172541B2 Driver circuit having load-independent slew rate 失效
标题翻译：驱动电路具有负载独立的转换速率
公开(公告)号：US06172541B2
公开(公告)日：2001-01-09
申请号：US09152420
申请日：1998-09-14
申请人： William R. Young , Stuart W. Pullen
发明人： William R. Young , Stuart W. Pullen
IPC分类号： H03K512
CPC分类号： H04L25/028 , H03K19/00361 , H03K19/00384
摘要： Load-monitoring feedback is used to maintain the slew rate of a line driver circuit at a prescribed rate that is independent of the effective load of the line being driven. This load-monitoring feedback control makes it possible to drive the line with an amplified output signal that faithfully tracks the input signal and conforms with prescribed slew rate and rise/fall time specifications, irrespective of characteristics of the signal line, which may vary over a specified range of component values. In a first embodiment, slew rate control is effected by increasing or decreasing the amount of charge on a reference capacitor and thereby the drive current to an output driver FET, in accordance with the change in state of the output of an output terminal-monitoring voltage threshold comparator relative to termination of a prescribed (one-shot established) time window. In a second embodiment, slew rate control is effected by directly determining the length of time required for the output terminal to transition between first and second states, and adjusting the operation of the output driver FET based on whether the total time measurement is equal to, greater than or less than the slew rate window.
摘要翻译：负载监控反馈用于将线路驱动电路的转换速率保持在与驱动线路的有效负载无关的规定速率。该负载监测反馈控制使得可以用放大的输出信号来驱动线路，该放大的输出信号忠实地跟踪输入信号并且符合规定的转换速率和上升/下降时间规范，而与信号线的特性无关，其可以在一个指定范围的组件值。在第一实施例中，通过根据输出端子监视电压的输出状态的变化来增加或减少参考电容器上的电荷量，从而提供到输出驱动器FET的驱动电流来实现转换速率控制阈值比较器相对于规定（一次建立）时间窗口的终止。在第二实施例中，通过直接确定输出端子在第一和第二状态之间转变所需的时间长度以及基于总时间测量是否等于调整输出驱动器FET的操作来实现压摆率控制，大于或小于压摆率窗口。

28. 再颁专利

USRE36388E Sine/cosine generator and method 失效
标题翻译：正弦/余弦发生器和方法
公开(公告)号：USRE36388E
公开(公告)日：1999-11-09
申请号：US400811
申请日：1995-03-08
申请人： James G. Fox , William R. Young , David B. Chester
发明人： James G. Fox , William R. Young , David B. Chester
IPC分类号： G06F1/035 , G06F7/52 , G06F1/02
CPC分类号： G06F7/5338 , G06F1/0353 , G06F1/0356 , G06F2101/04 , G06F7/49994
摘要： A sine/cosine generator with coarse and fine angles having compressed sine and cosine read only memories (ROMS) by use of symmetry of coarse angles about .pi./4 and, optionally, symmetry of fine angles about 0. The output of the ROMs directly feed multiplexers for utilization of the compressed storage. Addressing of complementary coarse angles is with one's complementing of the address and of complementary fine angles is with two's commplementing of the address. Fine sines and cosines are stored in recoded version for direct use in multipliers for computations using the sum of angles formulas.
摘要翻译：具有粗糙和精细角度的正弦/余弦发生器，通过使用大约π/ 4的粗略角度的对称性和可选的约为0的微小角度的对称性，具有压缩的正弦和余弦只读存储器（ROMS）。ROM的输出直接馈送用于压缩存储器的多路复用器。互补粗角度的寻址是用地址的补充，互补精细角度是两个地址的补充。精细的正弦和余弦存储在重新编码的版本中，用于使用角度公式的和进行计算的乘法器。

29. 发明授权

US5965933A Semiconductor packaging apparatus 失效
标题翻译：半导体封装设备
公开(公告)号：US5965933A
公开(公告)日：1999-10-12
申请号：US654316
申请日：1996-05-28
申请人： William R. Young , Kenneth A. Ports
发明人： William R. Young , Kenneth A. Ports
IPC分类号： H01L23/12 , B81B1/00 , H01L21/304 , H01L23/48 , H01L23/485 , H01L29/40
CPC分类号： H01L24/10 , H01L21/304 , H01L23/481 , H01L24/13 , H01L2224/13 , H01L2224/13099 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12042 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , Y10S438/977
摘要： Semiconductor devices 340 are formed in semiconductor wafer 300. Contact pads 332 are formed in each die 330. An interconnect connects the contact pads 332 to die surface contact regions 210, 212. Scribe trenches 348 are formed in device wafer 300; corresponding trenches 358 are formed in cover wafer 360. The cover wafer 360 is thinned to open scribe trenches 348. Conductive vias 310-313 connect the contact pads 210, 212 to external surface bump contacts 333.
摘要翻译：半导体器件340形成在半导体晶片300中。接触焊盘332形成在每个管芯330中。互连将接触焊盘332连接到管芯表面接触区域210,212。在器件晶片300中形成划线沟槽348; 相应的沟槽358形成在覆盖晶片360中。覆盖晶片360变薄以打开划线沟槽348.导电通孔310-313将接触焊盘210,212连接到外表面凸点触点333。

30. 发明授权

US5570392A Phase generator 失效
标题翻译：相位发生器
公开(公告)号：US5570392A
公开(公告)日：1996-10-29
申请号：US456859
申请日：1995-06-01
申请人： William R. Young , David B. Chester
发明人： William R. Young , David B. Chester
IPC分类号： H03D7/16 , H03H17/06 , H04B1/26 , H04B1/30 , H04J1/05 , H04Q11/04 , H04L27/20
CPC分类号： H04B1/0021 , H03D7/165 , H03H17/06 , H04B1/0003 , H04B1/26 , H04B1/30 , H04J1/05 , H04Q11/04
摘要： A digital down converter with a programmable mixing down frequency and a programmable extraction bandwidth uses a ROM based sin/cos generator plus a programmable high decimation filter followed by a gain compensating scaling multiplier and a fixed FIR filter. Output format options are also programmable, and programming commands are serially loaded into registers. Various components may be isolated for efficient testing and also subsystem operation.
摘要翻译：具有可编程混频低频和可编程提取带宽的数字下变频器使用基于ROM的sin / cos发生器加上可编程高抽取滤波器，随后是增益补偿缩放乘法器和固定FIR滤波器。输出格式选项也是可编程的，并且编程命令被串行加载到寄存器中。可以隔离各种组件用于有效测试和子系统操作。

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