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21. 发明申请

US20090073634A1 Circuit board for mounting multilayer chip capacitor and circuit board apparatus including the multilayer chip capacitor 有权
标题翻译：用于安装多层片状电容器的电路板和包括多层片状电容器的电路板装置
公开(公告)号：US20090073634A1
公开(公告)日：2009-03-19
申请号：US12155583
申请日：2008-06-06
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/005
CPC分类号： H01L23/50 , H01G4/35 , H01L23/49838 , H01L2924/0002 , H01L2924/3011 , H05K1/0231 , H05K1/113 , H05K2201/0792 , H05K2201/09309 , H05K2201/0979 , H05K2201/10636 , Y02P70/611 , H01L2924/00
摘要： A circuit board including: a substrate having a mounting area for mounting a vertical multilayer chip capacitor having first and second external electrodes of a first polarity and a third external electrode of a second polarity; first to third pads arranged on the mounting area, the first and second pads having the first polarity and disposed separately from each other on the mounting area, the third pad having the second polarity and disposed between the first and second pads to be connected to the third external electrode; at least one first via formed in the substrate and connected to the first pad; at least one second via formed in the substrate and connected to the second pad; and a plurality of third vias formed in the substrate and connected to the third pad. The first via is disposed adjacent to the third pad relative to a central line of the first pad, the second via is disposed adjacent to the third pad relative to a central line of the second pad, one or more of the third vias are disposed adjacent to the first via relative to a central line of the third pad, and the rest of the third vias are disposed adjacent to the second via relative to the central line of the third pad.
摘要翻译：一种电路板，包括：具有用于安装具有第一极性的第一和第二外部电极和第二极性的第三外部电极的垂直多层片状电容器的安装区域的基板; 布置在安装区域上的第一至第三焊盘，第一和第二焊盘具有第一极性并且在安装区域上彼此分开设置，第三焊盘具有第二极性并且设置在第一焊盘和第二焊盘之间以连接到第三外部电极; 至少一个第一通孔，其形成在所述基板中并连接到所述第一焊盘; 至少一个第二通孔，形成在所述衬底中并连接到所述第二衬垫; 以及形成在基板中并连接到第三焊盘的多个第三通孔。第一通孔相对于第一焊盘的中心线设置成与第三焊盘相邻，第二通孔相对于第二焊盘的中心线设置为与第三焊盘相邻，第一通孔中的一个或多个邻近相对于第三焊盘的中心线移动到第一通孔，并且第三通孔的其余部分相对于第三焊盘的中心线设置成与第二通孔相邻。

22. 发明申请

US20080165469A1 Multilayer chip capacitor 有权
标题翻译：多层片式电容器
公开(公告)号：US20080165469A1
公开(公告)日：2008-07-10
申请号：US12003884
申请日：2008-01-03
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228 , H01G4/005
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232
摘要： A multilayer chip capacitor including: a capacitor body formed of a lamination of a plurality of dielectric layers and having a bottom surface that is a mounting area; a plurality of internal electrodes disposed to be opposite to each other, interposing a dielectric layer there between in the capacitor body and having one lead extended to the bottom surface, respectively; and three or more external electrodes formed on the bottom surface and connected to corresponding internal electrodes via the leads, wherein the internal electrodes are vertically disposed on the bottom surface, and the leads of the internal electrodes having a different polarity from each other, adjacent to each other in a lamination direction, are disposed to be always adjacent to each other in a horizontal direction.
摘要翻译：一种多层片状电容器，包括：电容器本体，其由多个电介质层的叠层形成，并且具有作为安装区域的底面; 设置成彼此相对的多个内部电极，在电容器主体之间插入介电层，并具有分别延伸到底面的一个引线; 以及三个或更多个外部电极，形成在底表面上并且经由引线连接到相应的内部电极，其中内部电极垂直设置在底部表面上，并且内部电极的引线彼此具有不同的极性，彼此在层叠方向上彼此沿水平方向布置。

23. 发明授权

US08117584B2 Method of implementing low ESL and controlled ESR of multilayer capacitor 有权
标题翻译：实现低ESL和多层电容控制ESR的方法
公开(公告)号：US08117584B2
公开(公告)日：2012-02-14
申请号：US12155805
申请日：2008-06-10
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： G06F17/50 , H01G4/30 , H01G4/055 , H01G4/288
CPC分类号： H01G4/232 , H01G4/30
摘要： Disclosed is a method of implementing controlled equivalent series resistance (ESR) having low equivalent series inductance (ESL) of a multi-layer chip capacitor which includes a plurality of internal electrodes each having first polarity or second polarity which is opposite to the first polarity, and dielectric layers each disposed between the internal electrodes of the first polarity and the second polarity, wherein the internal electrodes having the first polarity and the internal electrodes having the second polarity are alternated at least once to form one or more blocks being stacked.
摘要翻译：公开了一种实现具有低等效串联电感（ESL）的受控等效串联电阻（ESR）的方法，该多层片式电容器包括多个内部电极，每个内部电极具有与第一极性相反的第一极性或第二极性，以及电介质层，其各自设置在第一极性和第二极性的内部电极之间，其中具有第一极性的内部电极和具有第二极性的内部电极至少交替一次以形成一个或多个堆叠的块。

24. 发明授权

US07920370B2 Multilayer chip capacitor 有权
公开(公告)号：US07920370B2
公开(公告)日：2011-04-05
申请号：US11987835
申请日：2007-12-05
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228 , H01G4/248 , H01G4/06
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232
摘要： A multilayer chip capacitor includes: a capacitor body having first and second side surfaces and a bottom surface; a plurality of first and second internal electrodes in the capacitor body; first and second external electrodes having a first polarity and formed on the first and second side surfaces, respectively, to cover a respective lower edge of the side surfaces and to partially extend to the bottom surface; and a third external electrode having a second polarity and formed on the bottom surface. The internal electrodes are disposed in perpendicular to the bottom surface. Each of the first internal electrodes has a first lead drawn to the first side and bottom surfaces and a second lead drawn to the second side and bottom surfaces. Each of the second internal electrodes has a third lead drawn to the bottom surface.

25. 发明授权

US07733628B2 Multilayer chip capacitor 有权
标题翻译：多层片式电容器
公开(公告)号：US07733628B2
公开(公告)日：2010-06-08
申请号：US12005300
申请日：2007-12-27
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228 , H01G4/06
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30
摘要： A multilayer chip capacitor including: a capacitor body having a plurality of dielectric layers deposited therein and having a parallelepiped shape; at least three pairs of first and second external electrodes formed on two longer sides, the first and second external electrodes in each of the pairs having different polarities and opposing each other, and the first and second external electrodes on each of the longer sides arranged alternately with each other; and a plurality of first and second internal electrodes arranged alternately to interpose each of the dielectric layers, the first and second internal electrodes connected to the first and second external electrodes by leads, respectively, wherein the capacitor body has a length that is 2.5 times greater than a width thereof.
摘要翻译：一种多层片状电容器，包括：具有沉积在其中并具有平行六面体形状的多个电介质层的电容器主体; 形成在两个长边上的至少三对第一和第二外部电极，每对中的第一和第二外部电极具有不同的极性并且彼此相对，并且每个长边上的第一和第二外部电极交替布置彼此; 并且交替地布置多个第一和第二内部电极以分别插入每个电介质层，第一和第二内部电极分别通过引线连接到第一和第二外部电极，其中电容器主体具有2.5倍的长度比其宽度。

26. 发明申请

US20090244803A1 MULTILAYER CHIP CAPACITOR 有权
标题翻译：多层芯片电容器
公开(公告)号：US20090244803A1
公开(公告)日：2009-10-01
申请号：US12245856
申请日：2008-10-06
申请人： Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/30
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232
摘要： A multilayer chip capacitor includes a capacitor body including a first capacitor part and a second capacitor part, first and second external electrodes respectively formed on first and second longer side faces of the capacitor body, and third and fourth external electrodes respectively formed on first and second shorter side faces of the capacitor body. The first capacitor part includes first and second internal electrodes of opposite polarity, and the second capacitor part includes third and fourth internal electrodes of opposite polarity. The first to fourth internal electrodes each have one lead. The first to fourth external electrodes are respectively connected to the leads of the first to fourth internal electrodes. A series resonance frequency of the first capacitor part is different from that of the second capacitor part. Equivalent series resistance (ESR1) of the first capacitor part and the equivalent series resistance (ESR2) of the second capacitor part satisfy ERS1≧20 mΩ and 0.7(ESR1)≦ESR2≦1.3(ESR1).
摘要翻译：多层片状电容器包括电容器本体，其包括第一电容器部分和第二电容器部分，分别形成在电容器主体的第一和第二长侧面上的第一和第二外部电极，以及分别形成在第一和第二电极部分上的第三和第四外部电极电容器主体的较短侧面。第一电容器部分包括具有相反极性的第一和第二内部电极，并且第二电容器部分包括具有相反极性的第三和第四内部电极。第一至第四内部电极各有一个引线。第一至第四外部电极分别连接到第一至第四内部电极的引线。第一电容器部分的串联谐振频率与第二电容器部分的串联谐振频率不同。第一电容器部分的等效串联电阻（ESR1）和第二电容器部分的等效串联电阻（ESR2）满足ERS1> = 20mOmega和0.7（ESR1）<= ESR2 <= 1.3（ESR1）。

27. 发明申请

US20090034154A1 MULTILAYER CHIP CAPACITOR 有权
标题翻译：多层芯片电容器
公开(公告)号：US20090034154A1
公开(公告)日：2009-02-05
申请号：US12010018
申请日：2008-01-18
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/005
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30
摘要： A multilayer chip capacitor includes: a capacitor body; internal electrodes disposed in the capacitor body, each internal electrode having one or more lead; and external electrodes disposed on first and second side surfaces of the capacitor body to be electrically connected to the internal electrodes through the leads. The average number of leads in each internal electrode is smaller than half (½) of the total number of external electrodes. The leads of the internal electrodes having opposite polarities and adjacent in the lamination direction are disposed to be adjacent to each other as seen from the lamination direction. All the internal electrodes having the same polarity are electrically connected to each other in the capacitor.
摘要翻译：多层片状电容器包括：电容器本体; 设置在电容器本体中的内部电极，每个内部电极具有一个或多个引线; 以及设置在电容器主体的第一和第二侧面上的外部电极，以通过引线与内部电极电连接。每个内部电极的引线平均数小于外部电极总数的一半（1/2）。具有相反极性并且在层叠方向上相邻的内部电极的引线设置成从层叠方向看彼此相邻。具有相同极性的所有内部电极在电容器中彼此电连接。

28. 发明授权

US09036330B2 Multilayer chip capacitor and method of fabricating the same 有权
标题翻译：多层片式电容器及其制造方法
公开(公告)号：US09036330B2
公开(公告)日：2015-05-19
申请号：US12650134
申请日：2009-12-30
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/005 , H01G4/228 , H01G4/06 , H01G4/232 , H01G2/06 , H01G4/30 , H05K1/02 , H05K1/18
CPC分类号： H01G4/232 , H01G2/065 , H01G4/30 , H05K1/0231 , H05K1/0295 , H05K1/181 , H05K2201/0979 , H05K2201/09954 , Y10T29/435
摘要： A multilayer chip capacitor includes: a capacitor main body; a plurality of first and second inner electrodes; and m (m≧3) number of first and second outer electrodes. The plurality of first and second inner electrodes are connected with two outer electrodes positioned on both opposing surfaces and having the same polarity as that of the first and second inner electrodes, and classified into a plurality of groups depending on the locations of the outer electrodes connected to the first and second inner electrodes. At least one of two outer electrodes connected with inner electrodes of each group is different from an outer electrode connected with inner electrodes of a different group having the same polarity, and inner electrodes of one group are connected to outer electrodes connected with at least another one group so that all the inner electrodes belonging to the same polarity can be electrically connected.
摘要翻译：一种多层片状电容器包括：电容器主体; 多个第一和第二内部电极; 和m（m≥3）个数的第一和第二外部电极。多个第一和第二内部电极与位于两个相对表面上并且具有与第一和第二内部电极相同的极性的两个外部电极连接，并且根据连接的外部电极的位置被分成多个组到第一和第二内部电极。与每组的内部电极连接的两个外部电极中的至少一个不同于与具有相同极性的不同组的内部电极连接的外部电极，并且一组的内部电极连接到与至少另一个连接的外部电极使得属于相同极性的所有内部电极可以电连接。

29. 发明授权

US08213155B2 Multilayer chip capacitor 有权
标题翻译：多层片式电容器
公开(公告)号：US08213155B2
公开(公告)日：2012-07-03
申请号：US12340200
申请日：2008-12-19
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/005 , H01G4/228
CPC分类号： H01G4/35 , H01G4/012 , H01G4/232 , H01G4/30 , H01G4/38
摘要： There is provided a multilayer chip capacitor a multilayer chip capacitor including: a capacitor body including first and second capacitor units arranged therein; and first to fourth outer electrodes, wherein the first capacitor unit includes first and second inner electrodes, and the first capacitor unit includes a plurality of capacitor elements each having a pair of the first and second inner electrodes repeatedly laminated, the second capacitor unit includes third and fourth inner electrodes, and the second capacitor unit includes at least one capacitor element having a pair of the third and fourth inner electrodes repeatedly laminated, and at least one of the capacitor elements of the first capacitor unit is different from the other capacitor elements of the first capacitor unit in a lamination number of the first and second inner electrodes or a resonant frequency.
摘要翻译：提供了一种多层片状电容器，其包括：电容器主体，包括布置在其中的第一和第二电容器单元; 以及第一至第四外部电极，其中所述第一电容器单元包括第一和第二内部电极，并且所述第一电容器单元包括多个电容器元件，每个电容器元件具有反复层叠的一对第一和第二内部电极，所述第二电容器单元包括第三电极单元和第四内部电极，并且第二电容器单元包括至少一个电容器元件，其具有重复层叠的一对第三和第四内部电极，并且第一电容器单元的电容器元件中的至少一个与其他电容器元件不同第一电容器单元的第一和第二内部电极的叠层数或谐振频率。

30. 发明授权

US08194389B2 Multilayer chip capacitor including two terminals 有权
标题翻译：多层片式电容器包括两个端子
公开(公告)号：US08194389B2
公开(公告)日：2012-06-05
申请号：US12245865
申请日：2008-10-06
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/005 , H01G4/06 , H01G4/228
CPC分类号： H01G4/005 , H01G4/30
摘要： A multilayer chip capacitor includes a capacitor body including first and second longer side surfaces facing each other and first and second shorter side surfaces facing each other, first and second external electrodes respectively disposed at the first and second longer side surfaces, one or more first internal electrode pairs each including first and second internal electrodes, and one or more second internal electrode pairs each including third and fourth internal electrodes. The first to fourth internal electrodes each have one lead and are sequentially disposed in a stacked direction. The first to fourth internal electrodes have first to fourth leads respectively extending to first to fourth corners or portions adjacent thereto, and alternately connected with the first and second external electrodes. The first internal electrode pair and the second internal electrode pair cause a current to diagonally flow in opposite directions with respect to a long side direction.
摘要翻译：一种多层片状电容器包括：电容器主体，包括彼此面对的第一和第二较长侧表面;以及彼此面对的第一和第二短边表面，分别设置在第一和第二长边侧表面的第一和第二外部电极，每个电极对包括第一和第二内部电极，以及一个或多个第二内部电极对，每个包括第三和第四内部电极。第一至第四内部电极各自具有一个引线并且沿堆叠方向依次布置。第一至第四内部电极具有分别延伸到第一至第四角部或与其相邻的部分的第一至第四引线，并且与第一和第二外部电极交替连接。第一内部电极对和第二内部电极对使得电流相对于长边方向在相反的方向上斜向流动。

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