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21. 发明授权

US09130597B2 Non-volatile memory error correction 有权
标题翻译：非易失性存储器错误校正
公开(公告)号：US09130597B2
公开(公告)日：2015-09-08
申请号：US13667298
申请日：2012-11-02
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： H03M13/00 , H03M13/29 , H03M13/15 , G06F11/10 , H03M13/11 , H03M13/09
CPC分类号： H03M13/2909 , G06F11/1012 , H03M13/09 , H03M13/11 , H03M13/15 , H03M13/151 , H03M13/2927
摘要： Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (CAM) to perform logical address translation, b) a minimum CAM function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ECC) method as needed to correct for degrading storage, and/or d) serially generating ECC and using an ECC serial decoder to correct the data.
摘要翻译：可以通过以下方式实现写入限制性非易失性存储器中的数据存储的性能，寿命和数量：a）利用串行内容寻址存储器（CAM）来执行逻辑地址转换，b）执行擦除错误的最小CAM功能计数磨损均衡，c）根据需要越来越精细化二维纠错编码（ECC）方法以校正降级存储，和/或d）连续生成ECC并使用ECC串行解码器来校正数据。

22. 发明申请

US20140269015A1 USE OF HYDROCARBON NANORINGS FOR DATA STORAGE 审中-公开
标题翻译：用于数据存储的碳氢化合物的使用
公开(公告)号：US20140269015A1
公开(公告)日：2014-09-18
申请号：US14289104
申请日：2014-05-28
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： H01L29/06 , G11C11/21
CPC分类号： H01L29/0669 , B82Y10/00 , G11C11/14 , G11C11/161 , G11C11/44 , G11C13/025 , G11C2213/35 , H01F1/42 , H01L51/0052 , H01L51/0575
摘要： Hydro-carbon nanorings may be used in storage. Sufficiently cooled, an externally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of electrons. Similarly, an internally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of positrons. When matched streams of positrons and electrons are sufficiently compressed they may form Cooper pairs with magnetic moments aligned to the movement of the stream. Matched adjacent Cooper pairs of electrons and positrons may contain information within their magnetic moments, and as such, may transmit and store information with little or no energy loss. Information may be similarly encoded in magnetic moments of spins of pairs of positrons and electrons, not in the form of Cooper pairs.
摘要翻译：水碳纳米管可用于储存。足够冷却，可以使用外部氢掺杂的碳纳米来产生径向偶极场以包含电子流。类似地，内部氢掺杂的碳纳米可以用于产生径向偶极场以包含正电子流。当正电子和电子的匹配流被充分压缩时，它们可以形成具有与流的运动对准的磁矩的Cooper对。匹配的Cooper对电子和正电子可能包含其磁矩内的信息，因此，可以很少或没有能量损失传输和存储信息。信息可以类似地编码在正电子和电子对的旋转的磁矩中，而不是以Cooper对的形式。

23. 发明申请

US20140115422A1 NON-VOLATILE MEMORY ERROR CORRECTION 审中-公开
公开(公告)号：US20140115422A1
公开(公告)日：2014-04-24
申请号：US13659368
申请日：2012-10-24
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： G06F12/00 , H03M13/05
CPC分类号： H03M13/2909 , G06F11/1012 , H03M13/09 , H03M13/11 , H03M13/15 , H03M13/151 , H03M13/2927
摘要： Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (CAM) to perform logical address translation, b) a minimum CAM function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ECC) method as needed to correct for degrading storage, and/or d) serially generating ECC and using an ECC serial decoder to correct the data.

24. 发明申请

US20130127493A1 NEAREST NEIGHBOR SERIAL CONTENT ADDRESSABLE MEMORY 审中-公开
公开(公告)号：US20130127493A1
公开(公告)日：2013-05-23
申请号：US13739618
申请日：2013-01-11
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： G11C15/00 , H03K19/02
CPC分类号： G11C15/00 , G06K9/6276 , G11C15/04 , H03K19/02
摘要： A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs.

25. 发明授权

US08339824B2 Nearest neighbor serial content addressable memory 有权
标题翻译：最近的邻居串行内容可寻址内存
公开(公告)号：US08339824B2
公开(公告)日：2012-12-25
申请号：US12166960
申请日：2008-07-02
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G06K9/6276 , G11C15/04 , H03K19/02
摘要： A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs.
摘要翻译：可以使用数字设计和技术来实现曼哈顿最近邻内容可寻址存储器功能，通过用附加的存储器和计数器来增加串行内容可寻址存储器设计，用于并行地顺序累加的位，并且随后并行地比较串行输入的所有曼哈顿距离矢量和驻留在CAM中的所有对应矢量。除了曼哈顿距离之外，其他距离措施可以可选地与类似的技术和设计结合使用。

26. 发明申请

US20080320271A1 Hashing and Serial Decoding Techniques 有权
标题翻译：散列和串行解码技术
公开(公告)号：US20080320271A1
公开(公告)日：2008-12-25
申请号：US12199024
申请日：2008-08-27
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： G06F12/00
CPC分类号： G06F9/345
摘要： A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.
摘要翻译：一种用于通过以小于2的幂的初始数字开始产生所有N位无符号二进制数的列表的技术，连续地将该数乘以该幂2，并将最大非负数加到小于2的幂使得新数字不是已经生成的任何数字的重复，并且使用结果列表来生成有效的散列和串行解码硬件和软件。

27. 发明授权

US07249340B2 Adaptable circuit blocks for use in multi-block chip design 有权
标题翻译：适用于多块芯片设计的电路块
公开(公告)号：US07249340B2
公开(公告)日：2007-07-24
申请号：US10971609
申请日：2004-10-22
申请人： Laurence H. Cooke , Kumar Venkatramani
发明人： Laurence H. Cooke , Kumar Venkatramani
IPC分类号： G06F17/50
CPC分类号： G06F8/443 , G01R31/318342 , G01R31/318536 , G06F1/10 , G06F17/5045 , G06F17/5068 , G06F17/5077
摘要： Techniques for increasing flexibility in use of virtual component blocks include a method for hardening a foundation block, a pin-unscrambling methodology for semi-hardened virtual component blocks, and parameterizable virtual component blocks. A method for hardening a foundation block and utilizing it in a circuit design comprises the steps of defining a virtual component foundation block, hardening an interior region of the foundation block including at least the critical timing components such as the system bus. The foundation block has a “soft collar” for allowing interface parameters to be specified when the foundation block is incorporated into a circuit design. In addition, the foundation block may comprise an internal, hierarchical clocking scheme for even clock distribution and optimum performance. For example, all internal clock delays may be padded, except the longest one, so that the clock signal arrives at all relevant reference points within the foundation block at the same time.
摘要翻译：用于增加使用虚拟部件块的灵活性的技术包括用于硬化基础块的方法，用于半硬化虚拟部件块的引脚解扰方法以及可参数化的虚拟部件块。用于硬化基础块并在电路设计中利用它的方法包括以下步骤：定义虚拟部件基础块，硬化基础块的内部区域至少包括诸如系统总线的关键定时分量。基础块具有“软环”，用于在将基础块结合到电路设计中时允许指定接口参数。此外，基础块可以包括用于均匀时钟分配和最佳性能的内部分层时钟方案。例如，除了最长的时间之外，所有的内部时钟延迟可以被填充，使得时钟信号同时到达基础块内的所有相关参考点。

28. 发明授权

US06968514B2 Block based design methodology with programmable components 有权
标题翻译：具有可编程组件的基于块的设计方法
公开(公告)号：US06968514B2
公开(公告)日：2005-11-22
申请号：US09812068
申请日：2001-03-19
申请人： Laurence H. Cooke , Kumar Venkatramani , Jin-Sheng Shyr
发明人： Laurence H. Cooke , Kumar Venkatramani , Jin-Sheng Shyr
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method for designing a circuit block includes the steps of selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, at least one of said circuit blocks being programmable; collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method; accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk; upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks (FEA); and, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, in compliance with the criteria and modified constraints without changing the selected circuit block and the processing method.
摘要翻译：一种用于设计电路块的方法包括以下步骤：选择要用于设计电路系统的多个预先设计的电路块，所述电路块中的至少一个是可编程的; 收集反映设计者关于预先设计的电路块的经验的数据，设计者的经验适应于处理方法; 以设计师的经验数据和可接受的风险程度的方式接受或拒绝电路系统的设计; 在接受时，形成包含每个电路块（FEA）的标准和修改约束的块规范; 并且在接受之后，在不改变所选择的电路块和处理方法的情况下，根据标准和修改的约束，形成用于将电路块部署在芯片的平面图上的块规范。

29. 发明授权

US06901562B2 Adaptable circuit blocks for use in multi-block chip design 有权
标题翻译：适用于多块芯片设计的电路块
公开(公告)号：US06901562B2
公开(公告)日：2005-05-31
申请号：US09766311
申请日：2001-01-18
申请人： Laurence H. Cooke , Kumar Venkatramani
发明人： Laurence H. Cooke , Kumar Venkatramani
IPC分类号： G01R31/3183 , G01R31/3185 , G06F1/10 , G06F9/45 , G06F17/50
CPC分类号： G06F8/443 , G01R31/318342 , G01R31/318536 , G06F1/10 , G06F17/5045 , G06F17/5068 , G06F17/5077
摘要： Techniques for increasing flexibility in use of virtual component blocks include a method for hardening a foundation block, a pin-unscrambling methodology for semi-hardened virtual component blocks, and parameterizable virtual component blocks. A method for hardening a foundation block and utilizing it in a circuit design comprises the steps of defining a virtual component foundation block, hardening an interior region of the foundation block including at least the critical timing components such as the system bus. The foundation block has a “soft collar” for allowing interface parameters to be specified when the foundation block is incorporated into a circuit design. In addition, the foundation block may comprise an internal, hierarchical clocking scheme for even clock distribution and optimum performance. For example, all internal clock delays may be padded, except the longest one, so that the clock signal arrives at all relevant reference points within the foundation block at the same time.
摘要翻译：用于增加使用虚拟部件块的灵活性的技术包括用于硬化基础块的方法，用于半硬化虚拟部件块的引脚解扰方法以及可参数化的虚拟部件块。用于硬化基础块并在电路设计中利用它的方法包括以下步骤：定义虚拟部件基础块，硬化基础块的内部区域至少包括诸如系统总线的关键定时分量。基础块具有“软环”，用于在将基础块结合到电路设计中时允许指定接口参数。此外，基础块可以包括用于均匀时钟分配和最佳性能的内部分层时钟方案。例如，除了最长的时间之外，所有的内部时钟延迟可以被填充，使得时钟信号同时到达基础块内的所有相关参考点。

30. 发明授权

US06701474B2 System and method for testing integrated circuits 有权
标题翻译：集成电路测试系统和方法
公开(公告)号：US06701474B2
公开(公告)日：2004-03-02
申请号：US09888054
申请日：2001-06-22
申请人： Laurence H. Cooke , Christopher K. Lennard
发明人： Laurence H. Cooke , Christopher K. Lennard
IPC分类号： G01R2831
CPC分类号： G06F8/443 , G01R31/318342 , G06F17/5045 , G06F17/5068
摘要： A method of testing an integrated circuit including component blocks of random logic in a manufacturing environment is disclosed. The method includes the steps of performing built-in self tests, at least in part to test memory and data paths of the integrated circuit, performing diagnostics tests, at least in part to test the component blocks of random logic individually, performing stress tests using test vectors, at least in part to test the component blocks of random logic collectively; and performing scan-based tests of the integrated circuit, at least in part to test for structural faults in the integrated circuit.
摘要翻译：公开了一种在制造环境中测试包括随机逻辑的组件块的集成电路的方法。该方法包括执行内置自检的步骤，至少部分地测试集成电路的存储器和数据路径，执行诊断测试，至少部分地单独测试随机逻辑的组件块，使用测试向量，至少部分地集体测试随机逻辑的组件块; 以及对集成电路进行基于扫描的测试，至少部分地测试集成电路中的结构故障。

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