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21. 发明授权

US08399938B2 Stressed Fin-FET devices with low contact resistance 有权
标题翻译：具有低接触电阻的强调Fin-FET器件
公开(公告)号：US08399938B2
公开(公告)日：2013-03-19
申请号：US13405296
申请日：2012-02-25
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/088
CPC分类号： H01L29/7843 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858
摘要： An FET device includes a plurality of Fin-FET devices. The fins of the Fin-FET devices are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device.
摘要翻译： FET器件包括多个Fin-FET器件。 Fin-FET器件的鳍片由第一材料组成。 FET器件包括第二材料，其外延地融合鳍片。翅片相对于第二材料的上表面垂直凹入。 FET器件还包括形成在鳍片上方和第二材料上的连续硅化物层，以及覆盖该器件的应力衬垫。

22. 发明申请

US20120292705A1 SEMICONDUCTOR STRUCTURE HAVING UNDERLAPPED DEVICES 失效
标题翻译：具有底层设备的半导体结构
公开(公告)号：US20120292705A1
公开(公告)日：2012-11-22
申请号：US13108290
申请日：2011-05-16
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/092
CPC分类号： H01L27/1203 , H01L21/823864 , H01L21/823892
摘要： A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the. SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.
摘要翻译：一种半导体结构，其包括绝缘体上半导体（SOI）基板。 SOI衬底包括基极半导体层; 与基底半导体层接触的掩埋氧化物（BOX）层; 以及与BOX层接触的SOI层。半导体结构还包括相对于SOI层形成的电路，该电路包括在SOI层中具有源极和漏极延伸的N型场效应晶体管（NFET）和栅极; 以及在SOI层中具有源极和漏极延伸的P型场效应晶体管（PFET）和栅极。每个NFET和PFET下面也可以有一个阱。有一个非零的电偏压被施加到。 SOI衬底。 NFET扩展和PFET扩展中的一个可能分别相对于NFET栅极或PFET栅极被覆盖。

23. 发明申请

US20120025288A1 SOI Trench DRAM Structure With Backside Strap 有权
标题翻译： SOI沟槽DRAM结构带背面带
公开(公告)号：US20120025288A1
公开(公告)日：2012-02-02
申请号：US12847208
申请日：2010-07-30
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/8242 , H01L27/108 , H01L21/02
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： In one exemplary embodiment, a semiconductor structure including: a silicon-on-insulator substrate having of a top silicon layer overlying an insulation layer, where the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, where the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, where at least a first portion of the backside strap underlies the doped portion of the top silicon layer, where the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, where the second epitaxially-deposited material further at least partially overlies the first portion of the backside strap.
摘要翻译：在一个示例性实施例中，一种半导体结构，包括：绝缘体上硅衬底，其具有覆盖绝缘层的顶部硅层，其中所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在所述顶部硅层上的器件，其中所述器件耦合到所述顶部硅层的掺杂部分; 第一外延沉积材料的背面带，其中背侧带的至少第一部分位于顶部硅层的掺杂部分的下面，其中背面带在顶部硅层的第一端处耦合到顶部硅层的掺杂部分背面带和在背面带的第二端处的电容器; 以及第二外延沉积材料，其至少部分地覆盖在顶部硅层的掺杂部分上，其中第二外延沉积材料进一步至少部分地覆盖在背面带的第一部分上。

24. 发明申请

US20110291202A1 DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE 有权
标题翻译：减少接头泄漏的装置和方法
公开(公告)号：US20110291202A1
公开(公告)日：2011-12-01
申请号：US12789839
申请日：2010-05-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66628 , H01L21/26513 , H01L29/0847 , H01L29/41783 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834
摘要： A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions.
摘要翻译：用于减少半导体结中的结漏电的器件和方法包括在器件的源极/漏极区域中形成刻面的凸起结构。掺杂剂从小面凸起结构扩散到小平面凸起结构下面的基底中以形成源极/漏极区域。在刻面凸起结构上施加喷洒注入，以在源/漏区的衬底中产生多深度掺杂物分布。

25. 发明申请

US20110291100A1 DEVICE AND METHOD FOR FABRICATING THIN SEMICONDUCTOR CHANNEL AND BURIED STRAIN MEMORIZATION LAYER 有权
标题翻译：用于制造半导体通道和BURIED应力记忆层的装置和方法
公开(公告)号：US20110291100A1
公开(公告)日：2011-12-01
申请号：US12789792
申请日：2010-05-28
申请人： KANGGUO CHENG , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： KANGGUO CHENG , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L29/10 , H01L21/20
CPC分类号： H01L29/7847 , H01L21/02532 , H01L21/02664 , H01L21/26506 , H01L29/7841 , H01L29/785
摘要： A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.
摘要翻译：用于在半导体层中诱发应力的装置和方法包括提供具有形成在第一半导体层和第二半导体层之间的介电层的衬底，并且处理第二半导体层以形成非晶化材料。应力层沉积在第一半导体层上。将晶片退火以通过使非晶化材料重结晶来在第二半导体层中记忆应力。

26. 发明授权

US09461169B2 Device and method for fabricating thin semiconductor channel and buried strain memorization layer 有权
标题翻译：用于制造薄半导体沟道和埋层应变记忆层的器件和方法
公开(公告)号：US09461169B2
公开(公告)日：2016-10-04
申请号：US12789792
申请日：2010-05-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/00 , H01L21/84 , H01L29/78 , H01L21/02 , H01L21/265
CPC分类号： H01L29/7847 , H01L21/02532 , H01L21/02664 , H01L21/26506 , H01L29/7841 , H01L29/785
摘要： A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.
摘要翻译：用于在半导体层中诱发应力的装置和方法包括提供具有形成在第一半导体层和第二半导体层之间的介电层的衬底，并且处理第二半导体层以形成非晶化材料。应力层沉积在第一半导体层上。将晶片退火以通过使非晶化材料重结晶来在第二半导体层中记忆应力。

27. 发明授权

US08552487B2 SOI trench DRAM structure with backside strap 有权
标题翻译：具有背面带的SOI沟槽DRAM结构
公开(公告)号：US08552487B2
公开(公告)日：2013-10-08
申请号：US13568601
申请日：2012-08-07
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： A semiconductor structure includes a SOI substrate having a top silicon layer overlying an insulation layer, which overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, which device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlying the doped portion, the backside strap being coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlying the first portion.
摘要翻译：半导体结构包括：SOI衬底，其具有覆盖在底部硅层上的绝缘层的顶部硅层; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在顶部硅层上的器件，该器件耦合到顶部硅层的掺杂部分; 第一外延沉积材料的背面带，位于掺杂部分下面的背侧带的至少第一部分，背面带在背面带的第一端处耦合到顶部硅层的掺杂部分，并且连接到电容器在背面带的第二端; 以及第二外延沉积材料，其至少部分地覆盖在顶部硅层的掺杂部分上，第二外延沉积材料进一步至少部分地覆盖在第一部分上。

28. 发明申请

US20120299075A1 SOI Trench Dram Structure With Backside Strap 有权
标题翻译：具有背面表带的SOI沟槽结构
公开(公告)号：US20120299075A1
公开(公告)日：2012-11-29
申请号：US13568601
申请日：2012-08-07
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.
摘要翻译：在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在顶部硅层上的器件，该器件耦合到顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背面带的至少第一部分位于掺杂部分的下面，背侧带在背面带的第一端和电容器处耦合到顶部硅层的掺杂部分在背面带的第二端; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。

29. 发明申请

US20120286329A1 SOI FET with embedded stressor block 审中-公开
标题翻译：具有嵌入式应力块的SOI FET
公开(公告)号：US20120286329A1
公开(公告)日：2012-11-15
申请号：US13106900
申请日：2011-05-13
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L29/06 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： A method and a structure are disclosed relating to strained body UTSOI FET devices. The method includes forming voids in the source/drain regions that penetrate down into the substrate below the insulating layer. The voids are epitaxially filled with a semiconductor material of a differing lattice constant than the one of the SOI layer, thus becoming a stressor block, and imparts a strain onto the FET device body.
摘要翻译：公开了与应变体UTSOI FET器件有关的方法和结构。该方法包括在源极/漏极区域中形成穿透绝缘层下方的衬底中的空隙。空隙被外延填充有与SOI层不同的晶格常数的半导体材料，因此成为应力块，并且在FET器件本体上施加应变。

30. 发明申请

US20120276695A1 Strained thin body CMOS with Si:C and SiGe stressor 审中-公开
标题翻译：应变薄体CMOS与Si：C和SiGe应力
公开(公告)号：US20120276695A1
公开(公告)日：2012-11-01
申请号：US13098352
申请日：2011-04-29
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/8238
CPC分类号： H01L27/1211 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/845
摘要： A method is disclosed which is characterized as being process integration of raised source/drain and strained body for ultra thin planar and FinFET CMOS devices. NFET and PFET devices have their source/drain raised by selective epitaxy with in-situ p-type doped SiGe for the PFET device, and in-situ n-type doped Si:C for the NFET device. Such raised source/drains offer low parasitic resistance and they impart a strain onto the device bodies of the correct sign for respective carrier, electron or hole, mobility enhancement.
摘要翻译：公开了一种方法，其特征在于用于超薄平面和FinFET CMOS器件的凸起源极/漏极和应变体的处理集成。 NFET和PFET器件通过用于PFET器件的原位p型掺杂SiGe的选择性外延以及用于NFET器件的原位n型掺杂Si：C来提高其源极/漏极。这种升高的源极/漏极提供低的寄生电阻，并且它们对于相应的载流子，电子或空穴，迁移率增强赋予了正确符号的器件体上的应变。

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