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21. 发明公开

EP1293888A2 Methods and circuitry for implementing first-in first-out structure 有权
标题翻译：的方法和电路，用于执行一个FIFO结构
公开(公告)号：EP1293888A2
公开(公告)日：2003-03-19
申请号：EP02253454.9
申请日：2002-05-15
申请人： Broadcom Corporation
发明人： Momtaz, Afshin D. , Wang, Xin , Cao, Jun , Hairapetian, Armond , Chung, David
IPC分类号： G06F5/06
CPC分类号： G06F5/10 , G06F2205/106
摘要： Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

22. 发明公开

EP1158431A2 Method and apparatus for performing a binary search on an expanded tree 审中-公开
标题翻译：为在延长的树执行二进制搜索方法和装置
公开(公告)号：EP1158431A2
公开(公告)日：2001-11-28
申请号：EP01304484.7
申请日：2001-05-22
申请人： Broadcom Corporation
发明人： Cao, Jun , Smith, Brandon Carl , Ng, Eric
IPC分类号： G06F17/30
CPC分类号： G06F17/30985
摘要： A method and apparatus for searching an electronically stored table of information including a plurality of table entries and facilitating high speed searching of a table to provide a longest matching entry. The table searching method uses at least one memory unit having a table of information including a plurality of data entries. The table of information has a plurality of search keys associated with the plurality of data entries and the plurality of search keys form a tree structure based on a prefix length for each of the search keys. The plurality of search keys are expanded such that each of the plurality of search keys has two lowest level search keys associated therewith that cover a lowest level of the tree structure. A binary search of the lowest level search keys is performed based on a search value to determine a longest prefix match. A data entry of the plurality of data entries is output based on said longest prefix match. The method is also applicable to routing data in an internet router where the routing of data packets depends on address information stored in the table of information.
摘要翻译：一种用于搜索关于信息电子方式存储的表包括表条目的多个部分并加以促进的表的高速搜索，以提供一个最长的匹配条目的方法和装置。该表的搜索方法使用具有的信息的表的至少一个存储器单元，包括数据条目的复数。的信息的表具有数据条目的多元性和搜索关键字的所述多个相关联的搜索关键字的各个表单基于每个检索关键字的前缀长度的树结构。搜索键主体的多元化展开搜索做了每个搜索关键字的多个具有关联的两个最低级搜索键与有没有覆盖的树结构的最低水平。最低级搜索键的二进制搜索是基于确定性searchValue挖掘最长前缀匹配进行。数据条目的多个数据条目基于所述最长前缀匹配的输出。该方法因此适用于在互联网路由器，其中数据分组的路由取决于存储在信息表的地址信息路由数据。

23. 发明公开

EP2403300A3 Multi-protocol communications receiver with shared analog front-end 有权转让
标题翻译：多协议通信接收机具有共享模拟前端设备
公开(公告)号：EP2403300A3
公开(公告)日：2015-12-23
申请号：EP11005272.7
申请日：2011-06-28
申请人： Broadcom Corporation
发明人： Telang, Vivek , Chen, Hong , Parthasarathy, Vasudevan , Cao, Jun , Momtaz, Afshin , Ghiasi, Ali , Chen, Chung-Jue
IPC分类号： H04W52/02 , H04B1/00 , H04B1/40
CPC分类号： H04L27/0002 , H04B1/0007 , H04B1/406
摘要： According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.

24. 发明授权

EP1694004B1 Traffic policing with programmable registers 有权转让
标题翻译：与可编程寄存器流量监控
公开(公告)号：EP1694004B1
公开(公告)日：2012-10-03
申请号：EP05025592.6
申请日：2005-11-23
申请人： Broadcom Corporation
发明人： Smith, Brandon Carl , Cao, Jun
IPC分类号： H04L12/56
CPC分类号： H04L47/29 , H04L47/10 , H04L47/20 , H04L47/21 , H04L47/31 , H04L49/103 , H04L49/205 , H04L49/351

25. 发明公开

EP2403300A2 Multi-protocol communications receiver with shared analog front-end 有权转让
标题翻译： Mehrprotokoll-Kommunikationsempfängermit gemeinsam genutztem analogem前端
公开(公告)号：EP2403300A2
公开(公告)日：2012-01-04
申请号：EP11005272.7
申请日：2011-06-28
申请人： Broadcom Corporation
发明人： Telang, Vivek , Chen, Hong , Parthasarathy, Vasudevan , Cao, Jun , Momtaz, Afshin , Ghiasi, Ali , Chen, Chung-Jue
IPC分类号： H04W52/02 , H04B1/00 , H04B1/40
CPC分类号： H04L27/0002 , H04B1/0007 , H04B1/406
摘要： According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.
摘要翻译：根据示例实施例，通信接收器可以包括被配置为放大接收到的信号的可变增益放大器（VGA），被配置为控制VGA的VGA控制器，耦合到该输入端的多个模数转换器 VGA，其中当所述通信接收器被配置为处理第一通信协议的信号时，所述多个ADC电路是可操作的，并且其中当所述通信接收器被配置为处理第二通信协议的信号时，只有所述ADC电路的子集可操作。

26. 发明授权

EP1306970B1 Current-controlled CMOS wideband amplifier circuits 有权
标题翻译： Stromgesteuerte CMOS-Breitbandverstärkerschaltungen
公开(公告)号：EP1306970B1
公开(公告)日：2007-08-08
申请号：EP02255506.4
申请日：2002-08-06
申请人： Broadcom Corporation
发明人： Yin, Guangming , Cao, Jun
IPC分类号： H03F1/42 , H03F3/45 , H03F3/193
CPC分类号： H03F1/14 , H03F1/483 , H03F2203/45018 , H03F2203/45512 , H03F2203/45554 , H03F2203/45714

27. 发明公开

EP1760885A2 Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth 有权转让
标题翻译：电流控制CMOS（C 3 MOS）集成全差分延迟可变延迟单元和高带宽
公开(公告)号：EP1760885A2
公开(公告)日：2007-03-07
申请号：EP06008842.4
申请日：2006-04-27
申请人： Broadcom Corporation
发明人： Cao, Jun
IPC分类号： H03K5/00
摘要： Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth. A novel implementation includes a wideband differential transistor pair and a cross-coupled differential transistor pair. The wideband differential transistor pair can be implemented with appropriate input and output impedances to extend its bandwidth for use in broadband applications. These two stages, (1) buffer stage (or data amplifier stage) and (2) cross-coupled differential pair stage, are both very fast operating stages. This design does not incur any increased loading to previous or subsequent stages in a device. In addition, there is no increase in the total amount of current that is required.
摘要翻译：电流控制CMOS（C 3 MOS）与可变延迟和高带宽全集成差分延迟单元。一种新颖的实施方式包括一个宽带差分晶体管对和交叉耦合的差分晶体管对。宽带差分晶体管对可以与适当的输入和输出阻抗被实现为扩展其带宽为宽带应用中使用。这两个阶段：（1）缓冲级（或数据放大器级）和（2）交叉耦合差动对阶段，是非常快速的两个操作阶段。这样的设计不会产生任何增加的负载到前面或后面阶段的设备。此外，还有在当前的总量没有增加，需要做。

28. 发明公开

EP1420511A1 Phase detector for extended linear response and highspeed data regeneration 审中-公开
标题翻译：电子邮件
公开(公告)号：EP1420511A1
公开(公告)日：2004-05-19
申请号：EP03026075.6
申请日：2003-11-12
申请人： Broadcom Corporation
发明人： Cao, Jun
IPC分类号： H03D3/24 , H03L7/00 , H04B10/00 , H04L7/033 , H04B10/14 , H03K19/21 , H04L25/06 , H03D3/00 , H03F3/08
CPC分类号： H03L7/14 , H03D13/003 , H03F3/08 , H03L7/087 , H03L7/091 , H03L7/113 , H04L7/033
摘要： Methods and circuits for phase detectors having extended linear and monotonic ranges of operation. Phase detectors consistent with the present invention include a REFERENCE output that has improved immunity to the timing relationship between data input and clock signals. This improved immunity results in extended linear and monotonic ranges of operations.
摘要翻译：具有延长的线性和单调操作范围的相位检测器的方法和电路。与本发明一致的相位检测器包括对数据输入和时钟信号之间的定时关系具有改进的抗扰性的参考输出。这种改善的免疫力导致延长的线性和单调的操作范围。

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