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    • 23. 发明授权
    • Parallel processing units on a substrate, each including a column of
memory
    • 在基板上的并行处理单元,每个包括一列存储器
    • US5325500A
    • 1994-06-28
    • US628916
    • 1990-12-14
    • Alan G. BellJohn LampingMichael Dixon
    • Alan G. BellJohn LampingMichael Dixon
    • G06F9/38G06F15/80G11C7/10G06F13/00
    • G11C7/1006G06F15/8015G06F9/38
    • Parallel processing circuitry on a substrate includes an array of memory elements in rows and columns. Row select circuitry can select the memory elements in any of the rows. Each column has respective processing circuitry to access its memory elements. The columns' processing circuitry can perform operations on data in parallel, so that each column and its processing circuitry form a processing unit. Data can be transferred to or from any of the columns. A column register can be connected so that data from a first column can be read, stored, and then written into a second column. Or a permutation network with connecting lines can be set up so that each connecting line can transfer data from one column to another. The column register can be connected to a shift register for transferring data to or from an external connection. Or the connecting lines of the permutation network can be set up for transferring data to or from the external connection. The processing circuitry of all the columns are connected to receive signals that control their operations in parallel. The processor can be used to perform value assignment search, with each processing unit storing data indicating a respective combination of values. Initially, an initial processing unit has a valid bit in its memory set to indicate that its combination of values is consistent with constraints. Then data from one processing unit can be copied to another, and modified either in the source or in the destination processing unit to obtain two respective subcombinations of values, with the valid bit remaining set. The processing units can perform operations in parallel to determine whether their respective combinations are consistent with a constraint. If a combination is inconsistent, the respective valid bit is cleared.
    • 衬底上的并行处理电路包括行和列中的存储器元件的阵列。 行选择电路可以选择任何行中的存储器元件。 每列具有各自的处理电路以访问其存储元件。 列的处理电路可以并行地对数据执行操作,使得每个列及其处理电路形成处理单元。 数据可以转移到或从任何列传输。 可以连接列寄存器,以便可以读取,存储第一列的数据并将其写入第二列。 或者可以设置具有连接线的置换网络,使得每条连接线可以将数据从一列传输到另一列。 列寄存器可以连接到移位寄存器,用于将数据传输到外部连接或从外部连接传输数据。 或者可以设置排列网络的连接线,以将数据传送到外部连接或从外部连接传输数据。 所有列的处理电路被连接以接收并行控制其操作的信号。 处理器可用于执行值分配搜索,每个处理单元存储指示值的相应组合的数据。 最初,初始处理单元在其存储器中具有有效位以指示其值的组合与约束一致。 然后来自一个处理单元的数据可以被复制到另一个处理单元,并且在源或目的地处理单元中进行修改以获得值的两个相应的子组合,其中有效位被设置。 处理单元可以并行执行操作,以确定它们各自的组合是否与约束一致。 如果组合不一致,相应的有效位将被清除。
    • 24. 发明授权
    • Massively parallel propositional reasoning
    • 大规模平行推理推理
    • US5088048A
    • 1992-02-11
    • US205125
    • 1988-06-10
    • Michael DixonJohan de KleerJohn O. Lamping
    • Michael DixonJohan de KleerJohn O. Lamping
    • G06F15/16G06F9/44G06F17/30G06N5/04
    • G06F8/313
    • Propositional reasoning is performed on a massively parallel processor, with sets of element value combinations being handled by separate processing units. A host processor operates as a problem solver generating requests for propositional reasoning, and also operates as an interface between the problem solver and the parallel processor. In response to a request that includes a formula, the interface provides one or more formulas such as justifications and class restrictions. The interface provides instructions to the parallel processor based on each of these formulas. The instruction based on each formula are provided so that the set of element value combinations handled by each processing unit is not divided or forked into two subsets until necessary. If possible, forking is avoided by forcing the value of an element to the only value consistent with the current formula. Furthermore, if no additional processing unit is available for forking, the current formula is kept on a queue of formulas, and the corresponding instructions are subsequently repeated. In this manner, the host processor orders the formulas into a sequence that reduces the number of processing units required. When necessary, a selected assumption is forced to one value to free processing units; its other value is considered subsequently by backtracking. Each element value is assigned one or more bit positions in each processing unit, but when the values in all the processing units are the same for a given element, its bit position may be reclaimed, to reduce memory requirements. The interface also responds to a request for results by sending instructions that use circuitry in the parallel processor to obtain a combined result from the processing units.