会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 29. 发明申请
    • Method, system, and apparatus for system level initialization
    • 用于系统级初始化的方法,系统和装置
    • US20060126656A1
    • 2006-06-15
    • US11011801
    • 2004-12-13
    • Mani AyyarSrinivas ChennupatyAkhilesh KumarDoddaballapur JayasimhaMurugasamy NachimuthuPhanindra Mannava
    • Mani AyyarSrinivas ChennupatyAkhilesh KumarDoddaballapur JayasimhaMurugasamy NachimuthuPhanindra Mannava
    • H04L12/42
    • H04L67/125H04L69/324
    • Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
    • 讨论了用于系统和组件在点对点架构中的多个初始化技术。 因此,这些技术允许根据平台(如桌面,移动,小型服务器,大型服务器等)的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数 ,存储器控制器,IO集线器等。此外,该技术有助于以正确的一组POC值加电,因此避免了多次热复位并提高了启动时间。 在一个实施例中,可以消除保存新值的寄存器,例如在复位期间驱动的配置值(CVDR)和在复位期间捕获的配置值(CVCR)。 例如,POC值可以来自以下内容:平台输入时钟到核心时钟比率,启用/禁用LT,可配置重新启动,刻录初始化模式,禁用超线程,系统BSP插槽指示和平台拓扑索引。
    • 30. 发明授权
    • Cache pollution avoidance instructions
    • 缓存污染回避说明
    • US06275904B1
    • 2001-08-14
    • US09053385
    • 1998-03-31
    • Srinivas ChennupatyShreekant S. ThakkarThomas HuffVladimir Pentkovski
    • Srinivas ChennupatyShreekant S. ThakkarThomas HuffVladimir Pentkovski
    • G06F1208
    • G06F12/0886G06F9/30018G06F9/30036G06F9/30047G06F12/0804G06F12/0888
    • A computer system and method for providing cache memory management. The computer system comprises a main memory having a plurality of main memory addresses each having a corresponding data entry, and a processor coupled to the main memory. At least one cache memory is coupled to the processor. The at least one cache memory has a cache directory with a plurality of addresses and a cache controller having a plurality of data entries corresponding to the plurality of addresses. The processor receives an instruction having an operand address and determines if the operand address matches one of the plurality of addresses in the cache directory. If so, the processor updates a data entry in the cache controller corresponding to the matched address. Otherwise, a data entry corresponding to the operand address in the main memory is updated.
    • 一种用于提供高速缓存存储器管理的计算机系统和方法。 计算机系统包括具有多个主存储器地址的主存储器,每个主存储器地址都具有对应的数据条目,以及耦合到主存储器的处理器。 至少一个高速缓存存储器耦合到处理器。 所述至少一个高速缓冲存储器具有具有多个地址的高速缓存目录和具有对应于所述多个地址的多个数据条目的高速缓存控制器。 处理器接收具有操作数地址的指令,并确定操作数地址是否匹配高速缓存目录中的多个地址之一。 如果是这样,则处理器更新对应于匹配地址的高速缓存控制器中的数据条目。 否则,更新与主存储器中的操作数地址相对应的数据条目。