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21. 发明授权

US5013385A Quad processor 失效
标题翻译：四核处理器
公开(公告)号：US5013385A
公开(公告)日：1991-05-07
申请号：US443039
申请日：1989-12-01
申请人： Joseph A. Maher , E. John Vowles , Joseph D. Napoli , Arthur W. Zafiropoulo , Mark W. Miller
发明人： Joseph A. Maher , E. John Vowles , Joseph D. Napoli , Arthur W. Zafiropoulo , Mark W. Miller
IPC分类号： H01J37/18 , H01L21/00 , H01L21/677
CPC分类号： H01L21/6719 , H01J37/185 , H01L21/67126 , H01L21/67196 , H01L21/67742 , Y10S414/141
摘要： The present invention includes plural plasma etching vessels and a wafer queuing station arrayed with a wafer transfer arm in a controlled environment. Wafers are movable within the controlled environment one at a time selectably between the several plasma vessels and the wafer queuing station without atmospheric or other exposure to that possible contamination of the moved wafers is prevented. The system is selectively operative in either single-step or multiple-step processing modes, and in either of the modes, the several plasma etching vessels are operable to provide a desirably high system throughput. In the preferred embodiment, the several plasma vessels and the queuing station are arrayed about a closed pentagonal locus with the wafer transfer arm disposed within the closed locus.Wafer processing in each vessel is regulated by a state controller for processing a plurality of wafers from a single cassette, contained within the vacuum environment of the plural plasma etching vessels and wafer queuing station, to provide an orderly and efficient throughput of wafers for diverse or similar processing in the plural vessels. In this manner a wafer can be processed as soon as a vessel becomes available.
摘要翻译：本发明包括多个等离子体蚀刻容器和在受控环境中排列有晶片传送臂的晶片排队台。晶片可在可控制的环境中可选地在几个等离子体容器和晶片排队台之间可选地被移动，而无需大气或其它暴露，从而可以防止移动的晶片的可能的污染。该系统选择性地以单步或多步处理模式操作，并且在任一模式中，几个等离子体蚀刻容器可操作以提供期望的高系统吞吐量。在优选实施例中，几个等离子体容器和排队台围绕封闭的五边形轨迹排列，其中晶片传送臂设置在闭合轨迹内。每个容器中的晶片处理由用于从多个等离子体蚀刻容器和晶片排队台的真空环境中包含的单个盒子处理多个晶片的状态控制器来调节，以提供用于不同或不同的等离子体类似的处理在多个船只。以这种方式，一旦容器变得可用就可以处理晶片。

22. 发明授权

US4381965A Multi-planar electrode plasma etching 失效
标题翻译：多平面电极等离子体蚀刻
公开(公告)号：US4381965A
公开(公告)日：1983-05-03
申请号：US337372
申请日：1982-01-06
申请人： Joseph A. Maher, Jr. , Arthur W. Zafiropoulo
发明人： Joseph A. Maher, Jr. , Arthur W. Zafiropoulo
IPC分类号： H01L21/302 , C23F4/00 , H01J37/32 , H01J37/34 , H01L21/00 , H01L21/3065 , H01L21/677 , C23C15/00
CPC分类号： H01L21/67069 , C23F4/00 , H01J37/32568 , H01J37/32577 , H01J37/32623 , H01J37/34 , H01L21/67778 , Y10S414/137
摘要： Dry plasma etching of a plurality of planar thin-film semiconductor wafers is effected simultaneously and uniformly in a relatively small chamber enveloping a vertically-stacked array of laminar electrode sub-assemblies each of which includes a pair of oppositely-excited electrode plates tightly sandwiching a solid insulating layer of dielectric material, the parallel sub-assemblies being vertically separated to subdivide the chamber into a plurality of reactor regions where RF discharges can excite a normally inert ambient gas to develop reactive plasma for simultaneous planar plasma etching or reactive ion etching (RIE) of all wafers within the several regions. The upper plates of the electrode sub-assemblies, which support the wafers during etching, are at any instant all maintained at the same potential, whether RF or ground in the different modes of operation, and fluid coolant is forced through a distribution of internal passageways in those support plates; all lower plates of the pairs are simultaneously maintained at the opposite potential, whether ground or RF, and the intervening insulating dielectric layers in the sub-assemblies are relatively thin while at the same time providing critical electrical isolation and curbing spurious discharge without serious electrical mismatching. Uncomplicated transport of individual wafers between vertically-stacked positions in a cassette and the stacked array of etching regions is accomplished from below by a reciprocatable arm which is receivable within accommodating slots recessed into the upper cooled electrode plates alongside one edge of the stacked array; programmed vertical movements of the cassette and electrode array allow for appropriate loading and unloading of wafers, and for proper orientation of the reactor regions in relation to the enclosing chamber and associated equipment.
摘要翻译：多个平面薄膜半导体晶片的干等离子体蚀刻在包围层状电极子组件的垂直堆叠阵列的较小室中同时且均匀地进行，每个层叠电极子组件包括一对相对激励的电极板，固体绝缘层的介电材料，平行的子组件被垂直分离以将室细分成多个反应器区域，其中RF放电可以激发正常惰性环境气体以开发用于同时平面等离子体蚀刻或反应离子蚀刻的反应性等离子体（RIE ）几个地区内的所有晶圆。在蚀刻期间支撑晶片的电极子组件的上板在任何时刻都保持在相同的电位，无论是在不同操作模式下的RF还是接地，并且流体冷却剂被迫通过内部通道的分布在那些支撑板上; 配对中的所有下板同时保持在相反的电位，无论是接地还是RF，并且子组件中的中间绝缘介电层相对较薄，同时提供关键的电隔离和遏制杂散放电，而不会出现严重的电不匹配。单个晶片在盒中的垂直堆叠位置和蚀刻区域的堆叠阵列之间的简单传输是从下面通过可往复运动的臂实现的，该可往复臂可容纳在沿堆叠阵列的一个边缘凹陷入上部冷却电极板的容纳槽内; 盒和电极阵列的编程垂直运动允许晶片的适当加载和卸载，以及反应器区域相对于封闭室和相关设备的适当取向。

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