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21. 发明授权

US5574942A Hybrid execution unit for complex microprocessor 失效
标题翻译：用于复杂微处理器的混合执行单元
公开(公告)号：US5574942A
公开(公告)日：1996-11-12
申请号：US602254
申请日：1996-02-15
申请人： Robert P. Colwell , David B. Papworth , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Stephen M. Coward , Grace C. Chen
发明人： Robert P. Colwell , David B. Papworth , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Stephen M. Coward , Grace C. Chen
IPC分类号： G06F9/302 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30014 , G06F9/3885
摘要： A hybrid execution unit for executing miscellaneous instructions in a single clock cycle. The execution unit receives either integer or floating point data, and performs manipulations of two incoming sources to produce a result source in conjunction with existing integer and floating point execution units.
摘要翻译：一种混合执行单元，用于在单个时钟周期内执行各种指令。执行单元接收整数或浮点数据，并执行两个输入源的操作以产生结合现有整数和浮点执行单元的结果源。

22. 发明授权

US5546597A Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution 失效
标题翻译：在执行无序指令执行的处理器中，使用多周期凸轮准备选择依赖于数据的指令
公开(公告)号：US5546597A
公开(公告)日：1996-08-13
申请号：US203050
申请日：1994-02-28
申请人： Robert W. Martell , Glenn J. Hinton , Michael A. Fetterman , David B. Papworth , Robert P. Colwell , Andrew F. Glew
发明人： Robert W. Martell , Glenn J. Hinton , Michael A. Fetterman , David B. Papworth , Robert P. Colwell , Andrew F. Glew
IPC分类号： G06F9/38 , G06F9/345
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： An instruction dispatch circuit is disclosed that improves instruction execution throughput for a processor. The instruction dispatch circuit comprises an instruction buffer with a plurality of instruction entries and a content addressable memory array having at least one cam entry corresponding to each instruction entry. Each cam entry stores at least one source tag for the corresponding instruction entry. The content addressable memory array matches to a result tag from an execution circuit over a result bus, wherein the execution circuit transfers the result tag over the result bus at least one clock cycle before transferring a corresponding result data value over the result bus. Each cam entry generates a cam match signal used to determine whether data dependent instruction are ready for dispatch.
摘要翻译：公开了一种提高处理器的指令执行吞吐量的指令调度电路。指令调度电路包括具有多个指令条目的指令缓冲器和具有对应于每个指令条目的至少一个凸轮条目的内容可寻址存储器阵列。每个凸轮条目存储用于相应指令条目的至少一个源标签。内容可寻址存储器阵列通过结果总线与来自执行电路的结果标签相匹配，其中执行电路在通过结果总线传送相应的结果数据值之前至少一个时钟周期在结果总线上传送结果标签。每个凸轮条目产生一个凸轮匹配信号，用于确定数据相关指令是否准备好进行发送。

23. 发明授权

US5452426A Coordinating speculative and committed state register source data and immediate source data in a processor 失效
标题翻译：在处理器中协调推测和提交的状态寄存器源数据和即时源数据
公开(公告)号：US5452426A
公开(公告)日：1995-09-19
申请号：US177240
申请日：1994-01-04
申请人： David B. Papworth , Glenn J. Hinton , Michael A. Fetterman , Robert P. Colwell , Andrew F. Glew
发明人： David B. Papworth , Glenn J. Hinton , Michael A. Fetterman , Robert P. Colwell , Andrew F. Glew
IPC分类号： G06F9/38 , G06F9/24 , G06F9/28
CPC分类号： G06F9/30167 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857
摘要： A mechanism for coordinating source data in a processor, wherein a decode circuit issues instructions comprising at least one immediate valid flag and at least one logical register source. The immediate valid flag indicates whether an immediate operand for the instruction is available on an immediate data bus, and the logical register source specifies a physical register or a committed state register. A speculative result data value and a speculative source valid flag are read from the physical register, and a committed result data value is read from the committed state register. The speculative result data value and the speculative source valid flag or the committed result data value and the committed source valid flag provide a source data value and a source data valid flag for scheduling an execution of the instruction.
摘要翻译：一种用于在处理器中协调源数据的机制，其中解码电路发出包括至少一个即时有效标志和至少一个逻辑寄存器源的指令。即时有效标志指示在立即数据总线上是否有指令的立即操作数可用，逻辑寄存器源指定物理寄存器或提交状态寄存器。从物理寄存器读取推测结果数据值和推测源有效标志，并从承诺状态寄存器读取提交结果数据值。推测结果数据值和推测源有效标志或提交结果数据值和提交的源有效标志提供源数据值和源数据有效标志，用于调度指令的执行。

24. 发明授权

US5588126A Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system 失效
标题翻译：在无序执行计算机系统上缓存存储数据的方法和装置
公开(公告)号：US5588126A
公开(公告)日：1996-12-24
申请号：US446030
申请日：1995-05-19
申请人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , David B. Papworth
发明人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , David B. Papworth
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3834
摘要： In an out-of-order execution computer system, a store buffer is conditionally signaled to output buffered store data of buffered memory store operations, when a buffered memory load operation is being executed. The determination on whether to signal the store buffer or not is made using control information that includes the allocation state of the store buffer at the time the memory load operation being executed was issued. The allocation state includes the identification of the buffer slot storing the last memory store operation stored into the store buffer, and the wraparound state of a circular wraparound allocation approach employed to allocate buffer slots to the memory store operations, at the time the memory load operation being executed was issued.
摘要翻译：在无序执行计算机系统中，当执行缓冲存储器加载操作时，存储缓冲器有条件地发信号通知缓冲存储器存储操作的缓冲存储数据。使用包含在执行存储器加载操作的时刻存储缓冲器的分配状态的控制信息来确定是否发出存储缓冲器的信号。分配状态包括存储存储到存储缓冲器中的最后存储器存储操作的缓冲器槽的标识，以及在存储器加载操作时用于将缓冲器时隙分配给存储器存储操作的循环环绕分配方法的环绕状态正在执行中。

25. 发明授权

US5826109A Method and apparatus for performing multiple load operations to the same memory location in a computer system 失效
标题翻译：用于对计算机系统中的相同存储器位置执行多个加载操作的方法和装置
公开(公告)号：US5826109A
公开(公告)日：1998-10-20
申请号：US747197
申请日：1996-11-12
申请人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , David B. Papworth , Robert W. Martell
发明人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , David B. Papworth , Robert W. Martell
IPC分类号： G06F9/38 , G06F12/08 , G06F13/18
CPC分类号： G06F12/0859 , G06F9/3824 , G06F9/3834
摘要： The present invention provides for executing load instructions with a processor having a non-blocking cache memory, wherein individual load operations are dispatched to the cache memory and the cache memory signals the prevent the load operation from being sent to external memory when the load operation misses the cache memory and there is already a currently pending bus cycle to the same cache line. This helps reduce bus traffic on the external bus.
摘要翻译：本发明提供用具有非阻塞高速缓冲存储器的处理器执行加载指令，其中单独的加载操作被分派到高速缓冲存储器，并且高速缓冲存储器发出信号，以防止当加载操作错过时将加载操作发送到外部存储器高速缓存存储器并且已经存在当前待处理的总线周期到同一高速缓存行。这有助于减少外部总线上的总线流量。

26. 发明授权

US5606670A Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system 失效
标题翻译：用于发信号通知存储缓冲器以在无序执行计算机系统上输出用于加载操作的缓冲存储数据的方法和装置
公开(公告)号：US5606670A
公开(公告)日：1997-02-25
申请号：US636173
申请日：1996-04-22
申请人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , David B. Papworth
发明人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , David B. Papworth
IPC分类号： G06F9/38 , G06F9/22
CPC分类号： G06F9/3834
摘要： Store forwarding circuitry is provided to an out-of-order execution processor having a store buffer of buffered memory store operations. The store forwarding circuitry conditionally forwards store data for a memory load operation from a variable subset of the buffered memory store operations that is functionally dependent on the time the memory load operation is issued, taking into account the execution states of these buffered memory store operations. The memory load operation may be issued speculatively and/or executed out-of-order. The execution states of the buffered memory store operations may be speculatively executed or committed. The data and address aspects of the memory store operations may be executed separately.
摘要翻译：存储转发电路被提供给具有缓冲存储器存储操作的存储缓冲器的无序执行处理器。考虑到这些缓冲存储器存储操作的执行状态，存储转发电路有条件地转发存储器加载操作的存储数据，该数据来自缓冲存储器存储操作的可变子集，该操作在功能上取决于发出存储器加载操作的时间。存储器加载操作可以推测性地和/或无序地执行。可以推测性地执行或提交缓冲存储器存储操作的执行状态。存储器存储操作的数据和地址方面可以分开执行。

27. 发明授权

US5664137A Method and apparatus for executing and dispatching store operations in a computer system 失效
标题翻译：用于在计算机系统中执行和调度存储操作的方法和装置
公开(公告)号：US5664137A
公开(公告)日：1997-09-02
申请号：US525499
申请日：1995-09-07
申请人： Jeffrey M. Abramson , Haitham Akkary , Atig A. Bajwa , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Joel Huang , Kris G. Konigsfeld , Paul D. Madland , Prem Pahlajrai
发明人： Jeffrey M. Abramson , Haitham Akkary , Atig A. Bajwa , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Joel Huang , Kris G. Konigsfeld , Paul D. Madland , Prem Pahlajrai
IPC分类号： G06F9/312 , G06F9/38 , G06F9/00
CPC分类号： G06F9/3889 , G06F9/30043 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for performing store operations that includes calculating the address and obtaining the data for the store operation. The address represents the memory location to which the data is to be stored. Once the address is calculated and the data obtained, the store operation is committed to processor state. The store operation may be dispatched to memory to complete the execution of the store operation.
摘要翻译：一种用于执行存储操作的方法和装置，包括计算地址并获得用于存储操作的数据。地址表示要存储数据的存储器位置。一旦计算了地址并获得了数据，存储操作就被提交到处理器状态。可以将存储操作调度到存储器以完成存储操作的执行。

28. 发明授权

US5471633A Idiom recognizer within a register alias table 失效
标题翻译：注册表中的成语识别器
公开(公告)号：US5471633A
公开(公告)日：1995-11-28
申请号：US205842
申请日：1994-03-01
申请人： Robert P. Colwell , Andrew F. Glew , David B. Papworth , Glenn J. Hinton , David W. Clift
发明人： Robert P. Colwell , Andrew F. Glew , David B. Papworth , Glenn J. Hinton , David W. Clift
IPC分类号： G06F9/30 , G06F9/38 , G06F7/00
CPC分类号： G06F9/3824 , G06F9/30112 , G06F9/3826 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A register alias table unit (RAT) with an idiom recognition mechanism for overriding partial width conditions stalls is described. A partial width stall condition occurs during the RAT renaming process when a logical source register being renamed is larger than the corresponding physical source register pointed to by a renaming table. An idiom recognizer detects uops that zero their logical destination register and sets and clears zero bits in an iRAT array accordingly. The zero bits indicate which portions of an entry's physical source register are known to be zeros. A partial width stall override mechanism overrides a partial width stall condition when the zero bits for the physical source register causing the partial width stall indicate that the "missing" portion of the physical source register contains zeros. The performance of a microprocessor implementing such a RAT renaming mechanism with an idiom recognizer is improved because common partial width stalls are avoided.
摘要翻译：描述了具有用于覆盖部分宽度条件失速的习惯识别机制的寄存器别名表单元（RAT）。当重新命名的逻辑源寄存器大于重命名表指向的相应物理源寄存器时，在RAT重命名过程期间发生部分宽度失速状况。成语识别器检测uops，使其逻辑目标寄存器为零，并相应地设置和清除iRAT阵列中的零位。零位指示条目的物理源寄存器的哪些部分已知为零。当导致部分宽度失速的物理源寄存器的零位指示物理源寄存器的“丢失”部分包含零时，部分宽度失速覆盖机制将覆盖部分宽度失速条件。通过习惯识别器实现这种RAT重命名机构的微处理器的性能得到改善，因为避免了普通的部分宽度档位。

29. 发明授权

US5778407A Methods and apparatus for determining operating characteristics of a memory element based on its physical location 失效
标题翻译：基于其物理位置来确定存储元件的操作特性的方法和装置
公开(公告)号：US5778407A
公开(公告)日：1998-07-07
申请号：US667241
申请日：1996-06-21
申请人： Andrew F. Glew , Glenn J. Hinton , David B. Papworth , Michael Alan Fetterman , Robert P. Colwell , Frederick Jay Pollack
发明人： Andrew F. Glew , Glenn J. Hinton , David B. Papworth , Michael Alan Fetterman , Robert P. Colwell , Frederick Jay Pollack
IPC分类号： G06F12/08 , G06F12/10 , G06F12/06
CPC分类号： G06F12/0888 , G06F12/1027 , G06F2212/206
摘要： A circuit comprising a number of range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory operating characteristics to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type, and the memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.
摘要翻译：包括多个范围寄存器和互补解码/匹配电路的电路被提供给处理器，用于确定物理地址的存储器类型，由此一旦物理地址在前面的执行阶段可用就允许确定存储器操作特性缓存访问。此外，存储器类型字段被提供给用于存储确定的存储器类型的数据和指令存储器子系统的每个地址转换后备缓冲器条目，并且存储器类型确定电路被布置在页面未命中处理器中，从而允许确定存储器类型同时确定物理地址。

30. 发明授权

US06047369A Flag renaming and flag masks within register alias table 失效
标题翻译：标志在注册表别名中重命名和标记掩码
公开(公告)号：US06047369A
公开(公告)日：2000-04-04
申请号：US204521
申请日：1994-02-28
申请人： Robert P. Colwell , Andrew F. Glew , Atiq A. Bajwa , Glenn J. Hinton , Michael A. Fetterman
发明人： Robert P. Colwell , Andrew F. Glew , Atiq A. Bajwa , Glenn J. Hinton , Michael A. Fetterman
IPC分类号： G06F9/32 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30032 , G06F9/30094 , G06F9/3013 , G06F9/30134 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A mechanism and method for renaming flags within a register alias table ("RAT") to increase processor parallelism and also providing and using flag masks associated with individual instructions. In order to reduce the amount of data dependencies between instructions that are concurrently processed, the flags used by these instructions are renamed. In general, a RAT unit provides register renaming to provide a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs, for instance) to eliminate false data dependencies between instructions that reduce overall superscalar processing performance for the microprocessor. The renamed flag registers contain several flag bits and various flag bits may be updated or read by different instructions. Also, static and dynamic flag masks are associated with particular instructions and indicate which flags are capable of being updated by a particular instruction and also indicate which flags are actually updated by the instruction. Static flag masks are used in flag renaming and dynamic flag masks are used at retirement. The invention also discovers cases in which a flag register is required that is a superset of the previously renamed flag register portion.
摘要翻译：一种用于重命名寄存器别名表（“RAT”）中的标志以增加处理器并行性并且还提供和使用与各个指令相关联的标志掩码的机制和方法。为了减少并发处理的指令之间的数据依赖性，这些指令使用的标志被重命名。通常，RAT单元提供寄存器重命名以提供比通常在给定宏架构的逻辑寄存器集（例如Intel架构或PowerPC或Alpha设计）内通常可用的更大的物理寄存器集，以消除指令之间的虚假数据依赖性这降低了微处理器的整体超标量处理性能。重命名的标志寄存器包含几个标志位，各种标志位可能被不同的指令更新或读取。此外，静态和动态标志掩码与特定指令相关联，并且指示哪些标志能够被特定指令更新，并且还指示哪些标志实际上被指令更新。在标志重命名中使用静态标志掩码，退休时使用动态标志掩码。本发明还发现需要作为先前重命名的标志寄存器部分的超集的标志寄存器的情况。

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