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21. 发明授权

US07868375B2 Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing 有权
公开(公告)号：US07868375B2
公开(公告)日：2011-01-11
申请号：US12618632
申请日：2009-11-13
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien Sheng Su , Yaw Wen Hu
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

22. 发明授权

US06855980B2 Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling 有权
标题翻译：半导体存储器阵列的浮动栅极存储单元具有低电阻源区和高源耦合
公开(公告)号：US06855980B2
公开(公告)日：2005-02-15
申请号：US10690204
申请日：2003-10-20
申请人： Chih Hsin Wang , Amitay Levi
发明人： Chih Hsin Wang , Amitay Levi
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8239 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction, and an apparatus formed thereby. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indentations or different widths. The trenches are filled with a conducting material to form blocks of the conducting material that constitute source regions with a first portion that is disposed adjacent to but insulated from the floating gate, and a second portion that this disposed over but insulated from the floating gate.
摘要翻译：一种在半导体衬底中形成浮置栅极存储单元的半导体存储器阵列的自对准方法，所述半导体衬底具有在所述衬底上基本上彼此平行的衬底上的多个间隔开的隔离区域和有源区域，以及由此形成的器件。浮动栅极形成在每个有源区域中。在行方向上，形成包括凹痕或不同宽度的沟槽。沟槽填充有导电材料，以形成构成源极区的导电材料块，其中第一部分邻近浮动栅极设置，但第一部分设置在与浮动栅极相隔但与浮动栅极绝缘的第二部分上。

23. 发明授权

US06773974B2 Method of forming a semiconductor array of floating gate memory cells and strap regions 有权
标题翻译：形成浮栅存储器单元和带区域的半导体阵列的方法
公开(公告)号：US06773974B2
公开(公告)日：2004-08-10
申请号：US10406917
申请日：2003-04-04
申请人： Chih Hsin Wang , Amitay Levi
发明人： Chih Hsin Wang , Amitay Levi
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L27/115
摘要： A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array. The array includes word lines and source lines that connect together control gates and source regions from memory cells contained in row within the array. The strap regions include word line strap cells through which the word lines traverse, wherein the word lines completely traverse across the strap regions, and source line strap cells in which the source lines terminate without completely traversing across the strap region. A first plurality of conductive metal contacts are each connected to one of the word lines in one of the word line strap cells. A second plurality of conductive metal contacts are each connected to one of the source lines in one of the source line strap cells.
摘要翻译：一种在半导体衬底中形成浮动栅极存储单元的半导体存储器阵列的自对准方法，以及在阵列内交错的带区域。该阵列包括字符串和源极线，其将控制栅极和源区域连接在阵列内的行中包含的存储器单元中。带区域包括字线条带单元，字线穿过该单元线，其中字线完全穿过带区域，以及源极线束带单元，其中源极线终止，而不完全穿过带区域。第一多个导电金属触点各自连接到一个字线条带单元中的一条字线。第二多个导电金属触点各自连接到源极线束带单元之一中的源极线之一。

24. 发明授权

US06727545B2 Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling 有权
公开(公告)号：US06727545B2
公开(公告)日：2004-04-27
申请号：US09916555
申请日：2001-07-26
申请人： Chih Hsin Wang , Amitay Levi
发明人： Chih Hsin Wang , Amitay Levi
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction, and an apparatus formed thereby. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indentations or different widths. The trenches are filled with a conducting material to form blocks of the conducting material that constitute source regions with a first portion that is disposed adjacent to but insulated from the floating gate, and a second portion that this disposed over but insulated from the floating gate.

25. 发明授权

US07927994B1 Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing 有权
标题翻译：具有浮置栅极，控制栅极，选择栅极和具有悬垂在浮动栅极上的擦除栅极的分流门非易失性闪存单元，阵列和制造方法
公开(公告)号：US07927994B1
公开(公告)日：2011-04-19
申请号：US12961193
申请日：2010-12-06
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： H01L21/4763
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译：改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间和底物中的第二区域。单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。擦除栅极具有在浮动栅极上延伸的突出端。悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

26. 发明授权

US07851846B2 Non-volatile memory cell with buried select gate, and method of making same 有权
标题翻译：具有埋选择栅极的非易失性存储单元及其制造方法
公开(公告)号：US07851846B2
公开(公告)日：2010-12-14
申请号：US12327114
申请日：2008-12-03
申请人： Nhan Do , Hieu V. Tran , Amitay Levi
发明人： Nhan Do , Hieu V. Tran , Amitay Levi
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L29/42328 , H01L27/11521 , H01L29/42336 , H01L29/7885
摘要： A memory device, and method of making the same, in which a trench is formed into the surface of a semiconductor substrate. Source and drain regions define a channel region there between. The drain is formed under the trench. The channel region includes a first portion that extends along a bottom wall of the trench, a second portion that extends along a sidewall of the trench, and a third portion that extends along the surface of the substrate. The floating gate is disposed over the channel region third portion. The control gate is disposed over the floating gate. The select gate is at least partially disposed in the trench and adjacent to the channel region first and second portions. The erase gate disposed adjacent to and insulated from the floating gate.
摘要翻译：一种存储器件及其制造方法，其中沟槽形成在半导体衬底的表面中。源区和漏区定义其间的通道区。漏极形成在沟槽下方。沟道区域包括沿着沟槽的底壁延伸的第一部分，沿着沟槽的侧壁延伸的第二部分和沿着衬底的表面延伸的第三部分。浮动栅极设置在沟道区域第三部分上。控制栅极设置在浮动栅上。选择栅极至少部分地设置在沟槽中并且邻近沟道区第一和第二部分。擦除栅极邻近并与浮栅隔绝。

27. 发明申请

US20090039410A1 Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing 审中-公开
标题翻译：分闸门非挥发性闪存单元，具有浮动栅极，控制栅极，选择栅极和具有悬垂在浮栅上的擦除栅极，阵列和制造方法
公开(公告)号：US20090039410A1
公开(公告)日：2009-02-12
申请号：US11834574
申请日：2007-08-06
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： H01L29/788
CPC分类号： H01L29/42328 , H01L27/11521 , H01L29/40114 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译：改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间和底物中的第二区域。单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。擦除栅极具有在浮动栅极上延伸的突出端。悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

28. 发明授权

US06703318B1 Method of planarizing a semiconductor die 有权
公开(公告)号：US06703318B1
公开(公告)日：2004-03-09
申请号：US10423270
申请日：2003-04-25
申请人： Amitay Levi , Gian Sharma
发明人： Amitay Levi , Gian Sharma
IPC分类号： H01L21302
CPC分类号： H01L21/31055 , H01L21/31053
摘要： A method of CMP planarizing a silicon dioxide layer on a silicon nitride in the semiconductor die is disclosed. A wafer has a plurality substantially identical semiconductor dies defined on the wafer. Each of the dies is separated from one another by a scribe line. A layer of silicon nitride is formed on the planar surface of the wafer where the silicon nitride has a top surface which is substantially parallel to the planar surface. A layer of silicon dioxide is deposited on the top surface with the silicon dioxide varying in height above the top surface. A mask is formed across the wafer, including on the scribe line, where the mask has a plurality of locations with each location having a differing density of gap-to-pillar ratio, which is proportional to the height of the silicon dioxide above the top surface. The silicon dioxide is anisotropically etched through each gap of the mask across the entire wafer where each gap is etched by the same amount in the height direction. CMP is then used to planarize the silicon dioxide to the top surface of the silicon nitride across the entire wafer.

29. 发明授权

US08384147B2 High endurance non-volatile memory cell and array 有权
标题翻译：高耐久性非易失性存储单元和阵列
公开(公告)号：US08384147B2
公开(公告)日：2013-02-26
申请号：US13097766
申请日：2011-04-29
申请人： Nhan Do , Amitay Levi
发明人： Nhan Do , Amitay Levi
IPC分类号： H01L29/792 , H01L29/788 , G11C7/00
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/3418 , H01L21/28273 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： Systems of electrically programmable and erasable memory cell are disclosed. In one exemplary implementation, a cell may have two storage transistors in a substrate of semiconductor material of a first cooductivity type The first storage transistor is of the type having a first region and a second region each of a second conductivity type in the substrate The second storage transistor is of the type having a third region and a fourth region each of a second conductivity type in the substrate. Arrays formed of such memory cells and non-volatile memory cells are also disclosed.
摘要翻译：公开了电可编程和可擦除存储单元的系统。在一个示例性实施方式中，单元可以在第一共同类型的半导体材料的衬底中具有两个存储晶体管。第一存储晶体管是具有第一区域的类型和在衬底中的每个第二导电类型的第二存储晶体管第二存储晶体管存储晶体管是在基板中具有第三区域和第四导电类型的第四区域的类型。还公开了由这样的存储器单元和非易失性存储单元形成的阵列。

30. 发明申请

US20110127599A1 Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing 审中-公开
标题翻译：具有浮动门的分闸门非易失性闪存单元，控制门，选择门和具有悬浮在浮动门上的擦除门，阵列和制造方法
公开(公告)号：US20110127599A1
公开(公告)日：2011-06-02
申请号：US13023443
申请日：2011-02-08
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： H01L29/788
CPC分类号： H01L29/42328 , H01L27/11521 , H01L29/40114 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译：改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间和底物中的第二区域。单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。擦除栅极具有在浮动栅极上延伸的突出端。悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

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