专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US5781025A Method for testing an electronic circuit by logically combining clock signals, and an electronic circuit provided with facilities for such testing 失效
标题翻译：通过逻辑地组合时钟信号来测试电子电路的方法，以及具有用于这种测试的设施的电子电路
公开(公告)号：US5781025A
公开(公告)日：1998-07-14
申请号：US674523
申请日：1996-07-02
申请人： Manoj Sachdev , Botjo Atzema
发明人： Manoj Sachdev , Botjo Atzema
IPC分类号： G01R31/316 , G01R31/28 , G01R31/30 , H03K19/00 , G01R25/00
CPC分类号： G01R31/30
摘要： An electronic circuit has a plurality of nodes at which a plurality of clock signals are present in operational use. The clock signals should have a pre-determined timing relationship amongst themselves. The circuit includes logic circuitry having inputs connected to the nodes and having an output to provide a pulse train. Any discrepancy between the actual and ideal pulse trains indicates a fault.
摘要翻译：电子电路具有多个节点，在操作使用中存在多个时钟信号。时钟信号应该在它们之间具有预定的时序关系。该电路包括逻辑电路，其具有连接到节点的输入端并具有提供脉冲串的输出。实际脉冲串和理想脉冲串之间的任何差异表示故障。

22. 发明授权

US5625300A Separate I.sub.DDQ -testing of signal path and bias path in an IC 失效
标题翻译：在IC中分离信号路径和偏置路径的IDDQ测试
公开(公告)号：US5625300A
公开(公告)日：1997-04-29
申请号：US355569
申请日：1994-12-14
申请人： Manoj Sachdev
发明人： Manoj Sachdev
IPC分类号： G01R31/28 , G01R31/30 , G01R31/316 , G11C29/04 , H01L21/822 , H01L27/04 , G01R31/26
CPC分类号： G01R31/2882 , G01R31/3004 , G01R31/3008
摘要： An IC is tested through I.sub.DDQ -measurements. The IC's substrate includes a region of a conductivity type with a supply node for supply of the circuit and with a biasing node for connection to a biasing voltage to bias the region. I.sub.DDQ -testing of the circuit is conducted while the supply node and the biasing node are galvanically disconnected to separate the contribution to the quiescent current from the circuit functionality features from the contribution to the quiescent current from the biasing features.
摘要翻译： IC通过IDDQ测量进行测试。 IC的衬底包括导电类型的区域，具有用于供应电路的供电节点和用于连接到偏置电压以偏置该区域的偏置节点。电源的IDDQ测试在电源节点和偏置节点电流断开的同时进行，以将来自电路功能特征的静态电流的贡献与偏置特性对静态电流的贡献分离。

23. 发明授权

US5495448A Memory testing through cumulative word line activation 失效
标题翻译：内存测试通过累积字线激活
公开(公告)号：US5495448A
公开(公告)日：1996-02-27
申请号：US399303
申请日：1995-03-06
申请人： Manoj Sachdev
发明人： Manoj Sachdev
IPC分类号： G01R31/28 , G11C8/04 , G11C8/12 , G11C29/00 , G11C29/34 , G11C29/50 , G11C7/00
CPC分类号： G11C29/50 , G11C29/34 , G11C8/04 , G11C8/12 , G11C11/41 , G11C2029/5006
摘要： An SRAM has a plurality of respective memory cells coupled to a respective one of a plurality of word lines and to a pair of bit lines. The SRAM comprises I.sub.DDQ test means to render the word lines active in parallel by cumulatively increasing a number of active ones among the word lines. This permits the writing of a specific logic state in all cells of a column through the tiny bit line drivers that are progressively assisted by the cells already written, thus avoiding the use of additional heavy write circuitry for I.sub.DDQ test purposes only.
摘要翻译： SRAM具有耦合到多个字线中的相应一个字线和一对位线的多个相应存储器单元。 SRAM包括IDDQ测试装置，用于通过累积增加字线中的活动字数来使字线平行活动。这允许通过由已经写入的单元逐步辅助的微小位线驱动器在列的所有单元中写入特定的逻辑状态，因此避免使用用于IDDQ测试目的的附加重写电路。

24. 发明授权

US09083320B2 Apparatus and method for electrical stability compensation 有权
标题翻译：电气稳定补偿装置及方法
公开(公告)号：US09083320B2
公开(公告)日：2015-07-14
申请号：US14032849
申请日：2013-09-20
申请人： Maofeng Yang , Nikolas Papadopoulos , William Wong , Manoj Sachdev
发明人： Maofeng Yang , Nikolas Papadopoulos , William Wong , Manoj Sachdev
IPC分类号： H05B37/02 , H05B39/04 , H03K3/012 , H05B33/08
CPC分类号： H03K3/012 , H03K17/223 , H05B33/0896
摘要： Provided is an apparatus and method for electrical stability compensation. The apparatus includes a drive transistor connecting a power supply to a load, a first variable capacitor having a gate and a source, and a switch transistor for controlling a connection between a programming signal source and a gate of the drive transistor. The gate of the first variable capacitor is connected to the gate of the drive transistor. The first variable capacitor is configured to draw a charge from the gate of the drive transistor during a driving phase for the load.
摘要翻译：提供一种用于电稳定性补偿的装置和方法。该装置包括将电源连接到负载的驱动晶体管，具有栅极和源极的第一可变电容器以及用于控制编程信号源与驱动晶体管的栅极之间的连接的开关晶体管。第一可变电容器的栅极连接到驱动晶体管的栅极。第一可变电容器被配置为在用于负载的驱动阶段期间从驱动晶体管的栅极引出电荷。

25. 发明授权

US08536898B2 SRAM sense amplifier 失效
标题翻译： SRAM读出放大器
公开(公告)号：US08536898B2
公开(公告)日：2013-09-17
申请号：US13151276
申请日：2011-06-02
申请人： David James Rennie , Manoj Sachdev
发明人： David James Rennie , Manoj Sachdev
IPC分类号： G01R19/00
CPC分类号： G11C7/065 , G11C11/413
摘要： A sense amplifier for use in a memory array having a plurality of memory cells is provided. The sense amplifier provides low power dissipation, rapid sensing and high yield sensing operation. The inputs to the sense amplifier are the differential bitlines of an SRAM column, which are coupled to the sense amplifier via the sources of two PMOS transistors. A CMOS latching element comprised of two NMOS transistors and the aforementioned PMOS transistors act to amplify any difference between the differential bitline voltages and resolve the output nodes of the sense amplifier to a full swing value. The latching element is gated with two additional PMOS transistors which act to block the latching operation until the sense amplifier is enabled. One or more equalization transistors ensure the latch remains in the metastable state until it is enabled. Once the latch has resolved it consumes no DC power, aside from leakage.
摘要翻译：提供了一种用于具有多个存储单元的存储器阵列中的读出放大器。感测放大器提供低功耗，快速感测和高产量感测操作。读出放大器的输入是SRAM列的差分位线，它们通过两个PMOS晶体管的源极耦合到读出放大器。由两个NMOS晶体管和上述PMOS晶体管组成的CMOS锁存元件用于放大差分位线电压之间的任何差异，并将读出放大器的输出节点解析为全摆幅值。闭锁元件门控有两个附加的PMOS晶体管，其用于阻止锁存操作，直到读出放大器被使能。一个或多个均衡晶体管确保闩锁保持在亚稳态，直到其被使能。一旦闩锁已经解决，除了泄漏外，它不会消耗直流电。

26. 发明申请

US20110255359A1 Sense-Amplification With Offset Cancellation For Static Random Access Memories 有权
标题翻译：用于静态随机存取存储器的偏移消除的感测放大
公开(公告)号：US20110255359A1
公开(公告)日：2011-10-20
申请号：US12757033
申请日：2010-04-08
申请人： Manoj Sachdev , Mohammad Sharifkhani , Jaspal Singh Shah , David Rennie
发明人： Manoj Sachdev , Mohammad Sharifkhani , Jaspal Singh Shah , David Rennie
IPC分类号： G11C7/06 , H03F3/16
CPC分类号： G11C7/062 , G11C2207/063 , G11C2207/104
摘要： An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on nodes of interest which are a function of transistor mismatch. The resulting voltage levels act to compensates for the transistor mismatch, thereby improving the reliability of the sense amplifier in the presence of process non-idealities. The offset cancellation scheme is applicable to numerous types of sense amplifiers.
摘要翻译：描述了用于感测放大的偏移消除方案。该方案由通过多相定时选择性地耦合到高电压和低电压电平的晶体管组成。这导致感兴趣的节点上的电压电平是晶体管不匹配的函数。所产生的电压电平用于补偿晶体管失配，从而在存在工艺非理想性的情况下提高读出放大器的可靠性。偏移消除方案适用于多种类型的读出放大器。

27. 发明申请

US20100110773A1 SRAM CELL WITHOUT DEDICATED ACCESS TRANSISTORS 有权
标题翻译：没有专用访问晶体管的SRAM单元
公开(公告)号：US20100110773A1
公开(公告)日：2010-05-06
申请号：US12494908
申请日：2009-06-30
申请人： Manoj Sachdev , David Rennie
发明人： Manoj Sachdev , David Rennie
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/412
摘要： A Static Random Access Memory (SRAM) cell without dedicated access transistors is described. The SRAM cell comprises a plurality of transistors configured to provide at least a pair of storage nodes for storing complementary logic values represented by corresponding voltages. The transistors comprise at least one bitline transistor, at least on wordline transistor and at least two supply transistors. The bitline transistor is configured to selectively couple one of the storage nodes to at least one corresponding bitline, the bitline for being shared by SRAM cells in one of a common row or column. The wordline transistor is configured to selectively couple another of the storage nodes to at least one corresponding wordline, the wordline for being shared by SRAM cells in the other of the common row or column. The supply transistors are configured to selectively couple corresponding ones of the storage nodes to a supply voltage.
摘要翻译：描述了没有专用存取晶体管的静态随机存取存储器（SRAM）单元。 SRAM单元包括多个晶体管，其被配置为提供至少一对存储节点，用于存储由对应电压表示的互补逻辑值。晶体管至少在字线晶体管和至少两个电源晶体管上包括至少一个位线晶体管。位线晶体管被配置为选择性地将存储节点之一耦合到至少一个相应的位线，该位线用于由公共行或列之一中的SRAM单元共享的位线。字线晶体管被配置为选择性地将另一个存储节点耦合到至少一个相应的字线，该字线由公共行或列中的另一个中的SRAM单元共享。电源晶体管被配置为选择性地将相应的存储节点耦合到电源电压。

28. 发明申请

US20090316505A1 Soft Error Robust Static Random Access Memory Cell Storage Configuration 有权
标题翻译：软错误鲁棒静态随机存取存储单元存储配置
公开(公告)号：US20090316505A1
公开(公告)日：2009-12-24
申请号：US12549757
申请日：2009-08-28
申请人： Manoj Sachdev , Shah M. Jahinuzzaman
发明人： Manoj Sachdev , Shah M. Jahinuzzaman
IPC分类号： G11C29/00 , G11C8/00 , G11C11/00
CPC分类号： G11C7/02 , G11C11/4125
摘要： A Static Random Access Memory (SRAM) cell storage configuration is provided with an improved robustness to radiation induced soft errors. The SRAM cell storage configuration comprises the following elements. First and second storage nodes are configured to store complementary voltages. Drive transistors are configured to selectively couple one of the first and second storage nodes to ground. Load transistors are configured to selectively couple the other one of the first and second storage nodes to a power supply. At least one stabilizer transistor is configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes, the redundant storage node being capable of restoring the first or second storage nodes in case of a soft error.
摘要翻译：静态随机存取存储器（SRAM）单元存储配置具有改善的对辐射诱导的软错误的鲁棒性。 SRAM单元存储配置包括以下元件。配置第一和第二存储节点以存储互补电压。驱动晶体管被配置为选择性地将第一和第二存储节点之一耦合到地。负载晶体管被配置为选择性地将第一和第二存储节点中的另一个耦合到电源。至少一个稳定器晶体管被配置为提供对应的冗余存储节点并限制第一和第二存储节点之间的反馈，冗余存储节点在软错误的情况下能够恢复第一或第二存储节点。

29. 发明授权

US07613067B2 Soft error robust static random access memory cells 有权
标题翻译：软错误鲁棒的静态随机存取存储单元
公开(公告)号：US07613067B2
公开(公告)日：2009-11-03
申请号：US11876223
申请日：2007-10-22
申请人： Manoj Sachdev , Shah M Jahinuzzaman
发明人： Manoj Sachdev , Shah M Jahinuzzaman
IPC分类号： G11C8/00
CPC分类号： G11C7/02 , G11C11/4125
摘要： A Static Random Access Memory (SRAM) cell is provided with an improved robustness to radiation induced soft errors. The SRAM cell includes the following elements. First and second storage nodes are configured to store complementary voltages. Access transistors are configured to selectively couple the first and second storage nodes to a corresponding bit line. Drive transistors are configured to selectively couple one of the first and second storage nodes to ground. Load transistors are configured to selectively couple the other one of the first and second storage nodes to a power supply. At least one stabilizer transistor is configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes. The redundant storage node is capable of restoring the first or second storage nodes in case of a soft error.
摘要翻译：静态随机存取存储器（SRAM）单元具有改善的对辐射诱导的软错误的鲁棒性。 SRAM单元包括以下元件。配置第一和第二存储节点以存储互补电压。接入晶体管被配置为选择性地将第一和第二存储节点耦合到对应的位线。驱动晶体管被配置为选择性地将第一和第二存储节点之一耦合到地。负载晶体管被配置为选择性地将第一和第二存储节点中的另一个耦合到电源。至少一个稳定器晶体管被配置为提供对应的冗余存储节点并限制第一和第二存储节点之间的反馈。冗余存储节点在软错误的情况下能够恢复第一或第二存储节点。

30. 发明申请

US20070217262A1 Segmented Column Virtual Ground Scheme In A Static Random Access Memory (SRAM) Circuit 失效
标题翻译：静态随机存取存储器（SRAM）电路中的分段列虚拟接地方案
公开(公告)号：US20070217262A1
公开(公告)日：2007-09-20
申请号：US11552655
申请日：2006-10-25
申请人： Manoj Sachdev , Mohammad Sharifkhani
发明人： Manoj Sachdev , Mohammad Sharifkhani
IPC分类号： G11C16/04
CPC分类号： G11C11/413 , G11C8/10 , G11C8/12 , G11C11/412
摘要： A static random access memory (SRAM) cell array is provided that reduces leakage current. The SRAM cell array is configured in a plurality of columns. Each of the columns comprises: a column virtual ground node; a column switch for selectively coupling the column virtual ground node to one of a ground or a nominal low voltage; and a plurality of segments. Each of the segments comprises: a segment virtual ground node; a plurality of SRAM cells including a virtual ground signal coupled to the segment virtual ground node; and a virtual ground switch for selectively coupling the segment virtual ground node to one of either a nominal low voltage or the column virtual ground node. A method for operating the SRAM cell array is also described.
摘要翻译：提供了一种减少漏电流的静态随机存取存储器（SRAM）单元阵列。 SRAM单元阵列被配置成多列。每列包括：虚拟虚拟接地节点; 用于选择性地将列虚拟接地节点耦合到接地或标称低电压之一的列开关; 和多个段。每个段包括：段虚拟接地节点; 多个SRAM单元，包括耦合到所述段虚拟接地节点的虚拟接地信号; 以及用于选择性地将段虚拟接地节点耦合到标称低电压或列虚拟接地节点之一的虚拟接地开关。还描述了用于操作SRAM单元阵列的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式