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21. 发明授权

US06888884B2 Method and system for dynamically inverting an asymmetric digital subscriber line (ADSL) system 失效
标题翻译：用于动态反转非对称数字用户线（ADSL）系统的方法和系统
公开(公告)号：US06888884B2
公开(公告)日：2005-05-03
申请号：US09755687
申请日：2001-01-05
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Gilles Toubol
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Gilles Toubol
IPC分类号： H04M11/06 , H04B1/38
CPC分类号： H04M11/062
摘要： A method and system for dynamically inverting an A symmetric Digital Subscriber Line (ADSL) system. The ADSL system includes a central exchange equipment (CE) connected to a service provider network and a user equipment (UE) connected to a user workstation. The CE and UE are interconnected by a PSTN link. The CE includes an ADSL transceiver and a splitter coupled between the CE transceiver and the PSTN link. The splitter includes a low-pass filter for separating low frequency voice signals from high frequency ADSL signals transmitted from the UE. In accordance with the method of the invention, an invert request message encoded as a tone sequence is generated by the UE and transmitted to the CE over the PSTN link. The tone-encoded invert request is received through the CE splitter low-pass filter and is decoded utilizing a tone decoder communicatively coupled between the CE splitter low-pass filter and the CE transceiver.
摘要翻译：一种用于动态反转A对称数字用户线（ADSL）系统的方法和系统。 ADSL系统包括连接到服务提供商网络的中央交换设备（CE）和连接到用户工作站的用户设备（UE）。 CE和UE通过PSTN链路相互连接。 CE包括ADSL收发器和耦合在CE收发器和PSTN链路之间的分离器。分离器包括用于将低频语音信号与从UE发送的高频ADSL信号分离的低通滤波器。根据本发明的方法，由UE产生编码为音调序列的反转请求消息，并通过PSTN链路传送到CE。通过CE分离器低通滤波器接收音调编码的反转请求，并且使用通信地耦合在CE分离器低通滤波器和CE收发器之间的音调解码器进行解码。

22. 发明授权

US06415061B1 Method of updating dictionaries in a data transmission system using data compression 失效
标题翻译：使用数据压缩更新数据传输系统中的字典的方法
公开(公告)号：US06415061B1
公开(公告)日：2002-07-02
申请号：US09067456
申请日：1998-04-28
申请人： Alain Benayoun , Patrick Michel , Jacques Fieschi , Jean-Francois Le Pennec
发明人： Alain Benayoun , Patrick Michel , Jacques Fieschi , Jean-Francois Le Pennec
IPC分类号： G06K946
CPC分类号： H03M7/3088
摘要： Method of updating dictionaries in a data transmission system wherein strings of characters have to be transmitted in a compressed form from the transmit device to the receive device, the transmit device having a transmit dictionary storing codewords associated with the strings of characters which are transmitted instead of the strings of characters, the receive device having a receive dictionary storing codewords associated with the strings of characters, both dictionaries being updated each time a new string of characters has to be transmitted so that their contents remain identical. This method stores a value into a specific field of the dictionary location in which the codeword associated with each string of characters is stored, this value corresponding to at least one parameter dependent on the string of characters; accesses a plurality of dictionary locations to determine which location has a value in this specific field which is closest to a target value, deletes the contents of the dictionary location containing the closest value, and uses this dictionary location to store the codeword corresponding to the new string of characters.
摘要翻译：在数据传输系统中更新字典的方法，其中字符串必须以压缩形式从发送设备发送到接收设备，发送设备具有发送字典，其存储与发送的字符串相关联的代码字，字符串，接收设备具有存储与字符串相关联的码字的接收字典，每当必须发送新的字符串字符时，两个字典都被更新，使得它们的内容保持相同。该方法将值存储到与每个字符串相关联的码字存储的字典位置的特定字段中，该值对应于取决于字符串的至少一个参数; 访问多个字典位置以确定哪个位置具有最接近目标值的该特定字段中的值，删除包含最近值的字典位置的内容，并使用该字典位置来存储对应于新的字符串

23. 发明授权

US06381253B1 Data transmission system and method for interconnecting sending and receiving analog devices primarily through data channels 失效
标题翻译：主要通过数据通道互连发送和接收模拟设备的数据传输系统和方法
公开(公告)号：US06381253B1
公开(公告)日：2002-04-30
申请号：US09046489
申请日：1998-03-23
申请人： Alain Benayoun , Patrick Michel , Dominique Vinot , Jean-Francois Le Pennec
发明人： Alain Benayoun , Patrick Michel , Dominique Vinot , Jean-Francois Le Pennec
IPC分类号： H04L1216
CPC分类号： H04N1/00312 , H04L12/2854 , H04N1/00281 , H04N1/32005 , H04N2201/0015 , H04Q11/0471 , H04Q2213/13031 , H04Q2213/13034 , H04Q2213/1309 , H04Q2213/13106 , H04Q2213/13174 , H04Q2213/13176 , H04Q2213/13179 , H04Q2213/13199 , H04Q2213/13202 , H04Q2213/13209 , H04Q2213/13292 , H04Q2213/1332
摘要： In a system and method of setting a data communication through an Integrated Service Digital Network (ISDN) between a transmitting analog device connected to a transmitting Terminal Adapter interfacing the ISDN network, a receiving analog device is connected to a receiving Terminal Adapter interfacing the ISDN network in a data communication system wherein a plurality of transmitting analog devices are connected and transmit data to a plurality of receiving analog devices primarily through a data channel and without device identification therein.
摘要翻译：在与连接到ISDN网络的发送终端适配器连接的发送模拟设备之间通过综合业务数字网（ISDN）设置数据通信的系统和方法中，接收模拟设备连接到接入ISDN网络的接收终端适配器在数据通信系统中，其中多个发送模拟设备被连接，并且主要通过数据信道向多个接收模拟设备发送数据，并且其中没有设备标识。

24. 发明授权

US5959992A Process for operating a communication equipment comprising a set of mechanically connected apparatuses being vertically and horizontally packed, and apparatus using the same 失效
标题翻译：用于操作包括垂直和水平包装的一组机械连接的设备的通信设备的操作，以及使用该通信设备的设备
公开(公告)号：US5959992A
公开(公告)日：1999-09-28
申请号：US771568
申请日：1996-12-20
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Jacques Fieschi
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Jacques Fieschi
IPC分类号： H04L12/44 , H04L12/54 , H04L12/28
CPC分类号： H04L12/5601 , H04L2012/445
摘要： A process for operating a communication equipment having a set of mechanically connected apparatuses being vertically and horizontally packed. Each apparatus comprises telecommunication functions such as echo cancellation, data compression or ISDN gateway, as well as vertical and horizontal mechanical and communication connections respectively allowing the vertical and horizontal exchanges of frames with neighboring apparatuses. The communication is based on a frame comprising n bytes routing header with n being an integer and an Asynchronous Transfer Mode (ATM) cell.
摘要翻译：一种用于操作具有垂直和水平包装的机械连接装置的通信设备的过程。每个装置包括电信功能，例如回波消除，数据压缩或ISDN网关，以及分别允许与相邻设备的帧的垂直和水平交换的垂直和水平机械和通信连接。通信基于包括n为整数的n字节路由报头和异步传输模式（ATM）小区的帧。

25. 发明授权

US5828891A Multilevel interrupt device 失效
标题翻译：多级中断装置
公开(公告)号：US5828891A
公开(公告)日：1998-10-27
申请号：US766689
申请日：1996-12-13
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel
IPC分类号： G06F13/24 , G06F9/48 , G06F13/26 , G06F9/46
CPC分类号： G06F13/26
摘要： The invention relates to multilevel interrupt device (10) using a common microprocessor interrupt signal (101) to process interrupt signals (INT1, . . . , INTN) received from N peripheral chips. This device (10) is connected to a microprocessor (100) and N peripheral chips (200,210,230) through data/address busses (108,110) and it is also connected to a memory (150) by an additional bus (112). An interrupt operation starts when any one of the peripheral chips activates an interrupt signal through OR gate (220) detected by the microprocessor. The invention avoids to involve the microprocessor in the determination of the interrupt requester except for the generation of a common start.sub.-- address decoded by logic (180) for starting interrupt operations and a common end.sub.-- address decoded by logic (190) for ending it. Owing to the start.sub.-- address and the interrupt signals (173,174) received, latch (170) generates a translated address to memory (150) through a multiplexer (160) to start the corresponding interrupt routine stored at this translated address. The activation of any one of the peripheral chips leads to the reading of the corresponding interrupt routine stored in the memory without requiring any action of the microprocessor. The number of interrupt routines depends on the possible combinations of the N interrupt signals.
摘要翻译：本发明涉及使用公共微处理器中断信号（101）来处理从N个外围芯片接收的中断信号（INT1，...，INTN）的多电平中断装置（10）。该设备（10）通过数据/地址总线（108,110）连接到微处理器（100）和N个外围芯片（200,210,230），并且还通过附加总线（112）连接到存储器（150）。当任何一个外围芯片通过由微处理器检测到的或门（220）激活中断信号时，中断操作开始。本发明避免涉及微处理器确定中断请求者，除了生成由用于启动中断操作的逻辑（180）解码的公共起始地址以及由逻辑（190）解码以用于结束它的公共结束地址。由于接收到起始地址和中断信号（173,174），锁存器（170）通过多路复用器（160）产生到存储器（150）的转换地址，以启动存储在该翻译地址处的相应中断程序。任何一个外围芯片的激活导致读取存储在存储器中的相应的中断程序，而不需要微处理器的任何动作。中断程序的数量取决于N个中断信号的可能组合。

26. 发明授权

US5771262A Impedance adapter for network coupler cable 失效
标题翻译：网络耦合器电缆阻抗适配器
公开(公告)号：US5771262A
公开(公告)日：1998-06-23
申请号：US716077
申请日：1996-09-19
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Henri Giuliano
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Henri Giuliano
IPC分类号： H04L25/02 , H03H11/28 , H04B3/02 , H04B3/00
CPC分类号： H04B3/02 , H03H11/28
摘要： The invention provides an impedance adapter that automaticaly switches to impedances that match network transmit/receive lines impedances (105,106) by a controlled switching of various impedances mounted serially/parallely with connected transmitter/receiver (100,101). For a high speed adapter, a balanced transmitter/receiver is required for limiting crosstalk effect due to the high transmission rate. Transmit/Receive impedance adaptation networks (102-103) are composed of serial/parallel networks of resistors and relay contacts that are switched independently by magnetic coils of an impedance switching circuit (110) and having values conformable to the various network impedances imposed by different national regulations. By using the principle of double deviation voltage technique, a measuring circuit (108) detects upward and downward voltages (VA,VB), VB amplified by 2 to generate an analog signal VS (VS=VA-2VB) to a control logic circuit (109). This circuit (109) determines if the resistors value selected by the magnetic coils of said impedance switching circuit (110) is equal or not equal to the impedance of the network lines (106,105). Thus, it compares VS to a voltage Vref (25) to generate an output which selects and activates the correct magnetic coil for changing or keeping equal the resistors of the receive/transmit impedance network (102,103) currently connected to the network lines (105,106).
摘要翻译：本发明提供一种阻抗适配器，其通过与所连接的发射机/接收机（100,101）串联/并行安装的各种阻抗的受控切换，自动切换到与网络发射/接收线路阻抗（105,106）匹配的阻抗。对于高速适配器，由于高传输速率，需要一个平衡的发射器/接收器来限制串扰效应。发射/接收阻抗适配网络（102-103）由电阻器和继电器触点的串联/并联网络组成，其由阻抗开关电路（110）的磁线圈独立地切换，并且具有与不同的不同网络阻抗匹配的值国家规定。通过使用双偏压电压技术的原理，测量电路（108）检测向上和向下的电压（VA，VB），VB放大2以产生模拟信号VS（VS = VA-2VB）到控制逻辑电路 109）。该电路（109）确定由所述阻抗开关电路（110）的磁线圈选择的电阻值是否等于网线（106,105）的阻抗。因此，它将VS与电压Vref（25）进行比较以产生输出，该输出选择并激活正确的磁线圈，用于改变或保持与当前连接到网络线路（105,106）的接收/发射阻抗网络（102,103）的电阻相等，。

27. 发明授权

US06996111B1 ATM node having local error correcting procedures 失效
标题翻译： ATM节点具有本地纠错程序
公开(公告)号：US06996111B1
公开(公告)日：2006-02-07
申请号：US09991000
申请日：2001-11-14
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Gilles Toubol
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Gilles Toubol
IPC分类号： H04L12/56
CPC分类号： H04Q11/0478 , H04L2012/5647 , H04L2012/5652
摘要： A node for a telecommunications network has a segmentation and reassembly module (SAR module) to perform segmentation and reassembly (SAR) on cells received by the node, the SAR module particularly providing Virtual Channel Identifier (VCI) and Virtual Path Identifier (VPI) translation (referred to as VCI/VPI translation), and has a direct memory access (DMA) mechanism for a storage external to the SAR module, the SAR module performing a first DMA access when the VCI/VPI translation are representative of an error code correcting (ECC) procedure to be carried out in the node, and the SAR module performing a second DMA access when the VCI/VPI translation corresponds to a message that does not require a local ECC procedure. A coder/decoder module performs an ECC procedure on the cells. A controller controls the coder/decoder module to perform an error correcting procedure in response to the detection of the first DMA access. The first DMA access uses a first address and the second DMA uses a second address. A Reed-Solomon coder-decoder or a Hamming coder-decoder may be used to perform the ECC procedure. An address decoder interprets the VCI/VPI identifiers to control whether or not an ECC procedure is done.
摘要翻译：用于电信网络的节点具有分段和重组模块（SAR模块），用于对由节点接收的小区执行分段和重组（SAR），SAR模块特别提供虚拟信道标识符（VCI）和虚拟路径标识符（VPI）转换（称为VCI / VPI转换），并且具有用于SAR模块外部的存储器的直接存储器访问（DMA）机制，当VCI / VPI转换代表纠错码时，SAR模块执行第一DMA访问（ECC）过程，并且当VCI / VPI转换对应于不需要本地ECC过程的消息时，SAR模块执行第二DMA访问。编码器/解码器模块对单元执行ECC过程。控制器控制编码器/解码器模块响应于第一DMA访问的检测来执行纠错过程。第一个DMA访问使用第一个地址，第二个DMA使用第二个地址。可以使用里德 - 所罗门编码器解码器或汉明编码器解码器来执行ECC过程。地址解码器解释VCI / VPI标识符以控制ECC过程是否完成。

28. 发明授权

US06804257B1 System and method for framing and protecting variable-lenght packet streams 有权
标题翻译：用于构建和保护可变长度数据包流的系统和方法
公开(公告)号：US06804257B1
公开(公告)日：2004-10-12
申请号：US09664931
申请日：2000-09-19
申请人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Gilles Toubol
发明人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Gilles Toubol
IPC分类号： H04J324
CPC分类号： H04L1/0061 , H04L1/0041 , H04L1/0072 , H04L1/008 , H04L1/0083 , H04L1/0085 , H04L7/048 , H04L7/10
摘要： A method and a system for framing variable-length packets in a data communications system are disclosed. The successive variable-length packets carrying users' data, are formed in a stream of chained packets comprising a header. Two CRC's are computed. One over the data and another one over the header however, including also the data CRC of the immediate previous packet, thus chaining successive packets in a steam of such packets. The invention also assumes that encryption is performed independently over header and corresponding CRC's and, on the other hand, over the data of current packet. The invention allows to better adapt the transportation of multi-media users' data in packets of variable-lengths while securing transport by chaining successive packets, thus preventing that accidental or malicious deletion and insertion of packets occur and remain undetected. Also, the invention permits that intermediate transport nodes, owning keys to decrypt headers, may perform packet add/drop multiplexing without requiring that users' data need to be decrypted on their way to their final destination.
摘要翻译：公开了一种用于在数据通信系统中成帧可变长度分组的方法和系统。携带用户数据的连续可变长度分组形成在包括报头的链式分组流中。计算两个CRC。然而，一个在数据上，另一个在报头上，还包括紧接在前的分组的数据CRC，从而链接这些分组的蒸汽中的连续分组。本发明还假定加密是在头部和对应的CRC上独立执行的，另一方面超过当前分组的数据。本发明允许通过链接连续分组来更好地适应多媒体用户数据在可变长度的分组中的传输，同时通过链接连续分组来保护传输，从而防止分组的意外或恶意删除和插入发生并且不被检测。此外，本发明允许拥有密钥来解密报头的中间传输节点可以执行分组添加/丢弃复用，而不需要在到达其最终目的地的途中对用户的数据进行解密。

29. 发明授权

US06704866B1 Compression and encryption protocol for controlling data flow in a network 有权
标题翻译：用于控制网络中的数据流的压缩和加密协议
公开(公告)号：US06704866B1
公开(公告)日：2004-03-09
申请号：US09187097
申请日：1998-11-05
申请人： Alain Benayoun , Jacques Fieschi , Patrick Michel , Jean-Francois Le Pennec
发明人： Alain Benayoun , Jacques Fieschi , Patrick Michel , Jean-Francois Le Pennec
IPC分类号： H04L900
CPC分类号： H04L63/0428
摘要： Process for controlling frames transporting data from a transmitting Terminal (DTE 1) to at least a receiving Terminal (DTE 2) through a plurality of consecutive nodes including a start access node (NODE 1) connected to said transmitting Terminal and at least an end access node (NODE 6) connected to said receiving Terminal and intermediary nodes (NODE 2 to NODE 5), with each data frame comprising one or several protocol layers respectively associated with one or several communication protocols of controlling the frame flow at each node; such a process consisting in adding to each data frame a Data Manipulation Layer (DML) defining the parameters necessary for managing the manipulation (compression and/or encryption) of each field of the data frame located after the DML, and adding to each data frame a Control message for transporting a control protocol defining new parameters to be used by some ones nodes for managing the communication flow through the consecutive nodes.
摘要翻译：用于控制通过包括连接到所述发射终端的起始接入节点（NODE 1）的多个连续节点将数据从发射终端（DTE 1）传输到至少接收终端（DTE 2）的帧的过程，以及至少一个终端接入连接到所述接收终端的节点（节点6）和中间节点（NODE 2到节点5），每个数据帧包括分别与控制每个节点处的帧流的一个或多个通信协议相关联的一个或多个协议层; 这种过程包括在每个数据帧中添加一个数据操作层（DML），该数据操作层定义了管理位于DML之后的数据帧的每个字段的操纵（压缩和/或加密）所需的参数，并且添加到每个数据帧控制消息，用于传送定义要由某些节点使用的新参数的控制协议，用于管理通过连续节点的通信流。

30. 发明授权

US06415363B1 Memory statistics counter and method for counting the number of accesses to a portion of memory 失效
标题翻译：存储器统计计数器和用于计数对存储器的一部分的访问次数的方法
公开(公告)号：US06415363B1
公开(公告)日：2002-07-02
申请号：US09512407
申请日：2000-02-24
申请人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Michel Verhaeghe
发明人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Michel Verhaeghe
IPC分类号： G06F1300
CPC分类号： G06F11/3409 , G06F11/348 , G06F2201/88
摘要： A memory statistic counter and method for counting the number of accesses (writes or reads) by a microprocessor (10) to at least a portion of a memory comprising a decoding logic unit (16) for providing a selection signal for selecting the portion of memory in response to control signals from the microprocessor, and adding logic units (18, 20, 22). The memory statistic counter includes a register which is incremented each time the portion of memory is accessed by the microprocessor and providing a registration signal when the number of accesses is equal to a predetermined number, and a queuing unit (44) for registering a value in a registering memory (50), such as a first-in-first-out (FIFO) memory, in response to the registration signal and providing an interrupt signal to the microprocessor when all locations of the registering memory have been filled, thereby indicating to the microprocessor that a defined number of accesses to the portion of memory has occurred.
摘要翻译：一种存储器统计计数器和方法，用于将由微处理器（10）接收（写入或读取）的数量计数到包括解码逻辑单元（16）的存储器的至少一部分，用于提供用于选择存储器部分的选择信号响应于来自微处理器的控制信号，以及添加逻辑单元（18,20,22）。存储器统计计数器包括每当存储器部分被微处理器访问并且当访问次数等于预定数量时提供注册信号而递增的寄存器，以及用于将值存储在其中的排队单元（44）诸如先入先出（FIFO）存储器的登记存储器（50），其响应于所述注册信号，并且在所述注册存储器的所有位置已经被填充时向微处理器提供中断信号，由此指示对存储器部分的定义数量的访问已经发生的微处理器。

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