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21. 发明申请

WO2005096320A2 THERMALLY CONDUCTIVE COMPOSITIONS AND METHODS OF MAKING THEREOF 审中-公开
标题翻译：导热组合物及其制备方法
公开(公告)号：WO2005096320A2
公开(公告)日：2005-10-13
申请号：PCT/US2005/010600
申请日：2005-03-29
申请人： GENERAL ELECTRIC COMPANY , ZHONG, Hong , GOWDA, Arun, Virupaksha , ESLER, David, Richard , PAISNER, Sara, Naomi
发明人： ZHONG, Hong , GOWDA, Arun, Virupaksha , ESLER, David, Richard , PAISNER, Sara, Naomi
IPC分类号： H01B3/00
CPC分类号： H01L23/3737 , B82Y30/00 , H01L23/42 , H01L24/29 , H01L2224/16225 , H01L2224/16227 , H01L2224/29 , H01L2224/2929 , H01L2224/29339 , H01L2224/29386 , H01L2224/29393 , H01L2224/29486 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/83102 , H01L2224/92125 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/01016 , H01L2924/01019 , H01L2924/0102 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/0104 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01057 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/09701 , H01L2924/12036 , H01L2924/12044 , H01L2924/157 , H01L2924/3011 , H01L2924/01031 , H01L2224/29105 , H01L2924/05432 , H01L2924/00014 , H01L2924/05032 , H01L2924/0503 , H01L2924/0532 , H01L2924/0542 , H01L2924/05342 , H01L2924/05341 , H01L2924/0536 , H01L2924/05442 , H01L2924/00
摘要： A composition comprising at least one liquid metal having a melting point less than 35°C; at least one electrically insulating solid filler comprising thermally conducting materials; at least one resin is provided. The composition is both thermally conducting and electrically insulating and has utility in the preparation of electronic devices comprising heat generating and heat dissipating structures. In one instance a composition is provided which comprises a liquid metal selected from the group consisting of gallium, gallium alloys, and mixtures thereof, a boron nitride particulate filler, and a silicone resin, wherein said liquid metal and particulate filler are present in a volume ratio of about 1:0.4 to about 1: 10. A method of making and using such a composition is also provided.
摘要翻译：一种组合物，其包含至少一种熔点低于35℃的液态金属; 至少一种电绝缘固体填料，包括导热材料; 提供至少一种树脂。该组合物是导热和电绝缘的，并且在制备包括发热和散热结构的电子器件中具有实用价值。在一种情况下，提供了一种组合物，其包含选自镓，镓合金及其混合物的液态金属，氮化硼颗粒填料和硅树脂，其中所述液态金属和颗粒填料存在于体积比例为约1:0.4至约1:10。还提供了制备和使用这种组合物的方法。

22. 发明申请

WO2005024942A1 THERMAL CONDUCTIVE MATERIAL UTILIZING ELECTRICALLY CONDUCTIVE NANOPARTICLES 审中-公开
标题翻译：使用电导电纳米材料的导热材料
公开(公告)号：WO2005024942A1
公开(公告)日：2005-03-17
申请号：PCT/US2004/025262
申请日：2004-08-05
申请人： GENERAL ELECTRIC COMPANY , TONAPI, Sandeep, Shrikant , ZHONG, Hong , SIMONE, Davide, Louis , FILLION, Raymond, Albert
发明人： TONAPI, Sandeep, Shrikant , ZHONG, Hong , SIMONE, Davide, Louis , FILLION, Raymond, Albert
IPC分类号： H01L23/42
CPC分类号： H01L24/29 , C09K5/14 , H01L23/373 , H01L23/3732 , H01L23/3737 , H01L24/83 , H01L2224/29 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29386 , H01L2224/29393 , H01L2224/29499 , H01L2224/32245 , H01L2224/8385 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/12044 , H01L2924/14 , H01L2924/00 , H01L2924/00014 , H01L2924/05442 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299
摘要： Thermal interface compositions (10) contain both non-electrically conductive micronsized fillers (18) and electrically conductive nanoparticles (20) blended with a polymer matrix (16). Such compositions increase the bulk thermal conductivity of the polymer composites as well as decrease thermal interfacial resistances that exist between thermal interface materials and the corresponding mating surfaces. Such compositions are electrically non-conductive. Formulations containing nanoparticles (20) also show less phase separation of micron-sized particles (18) than formulations without nanoparticles (20). Methods for increasing heat transfer include using such compositions between heat producing components (12) and heat sinks (14). Electronic components utilizing such compositions are also disclosed.
摘要翻译：热界面组合物（10）包含与聚合物基质（16）共混的非导电微粒化填料（18）和导电纳米颗粒（20）。这样的组合物增加了聚合物复合材料的体积热导率，并且降低了热界面材料和相应配合表面之间存在的热界面电阻。这样的组合物是非导电的。含有纳米颗粒（20）的制剂与没有纳米颗粒的制剂（20）相比，也显示微米级颗粒（18）的相分离较少。增加热传递的方法包括在发热部件（12）和散热器（14）之间使用这种组合物。还公开了使用这种组合物的电子元件。

23. 发明申请

WO2005023936A1 THIN BOND-LINE SILICONE ADHESIVE COMPOSITION AND METHOD FOR PREPARING THE SAME 审中-公开
标题翻译：薄粘结胶粘剂组合物及其制备方法
公开(公告)号：WO2005023936A1
公开(公告)日：2005-03-17
申请号：PCT/US2004/021660
申请日：2004-07-07
申请人： GENERAL ELECTRIC COMPANY , TONAPI, Sandeep, Shrikant , ZHONG, Hong , SCHATTENMANN, Florian, Johannes , DAVID, Jennifer, Lynn , SAVILLE, Kimberly, Marie , GOWDA, Arun Virupaksha , ELSER, David, Richard , PRABHAKUMAR, Ananth
发明人： TONAPI, Sandeep, Shrikant , ZHONG, Hong , SCHATTENMANN, Florian, Johannes , DAVID, Jennifer, Lynn , SAVILLE, Kimberly, Marie , GOWDA, Arun Virupaksha , ELSER, David, Richard , PRABHAKUMAR, Ananth
IPC分类号： C08L83/04
CPC分类号： C09J183/04 , C08G77/045 , C08G77/12 , C08G77/18 , C08G77/20 , C08G77/70 , C08K2201/005 , C08L83/04 , H01L23/3737 , H01L23/42 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/12044 , H01L2924/3011 , C08L83/00 , H01L2924/00
摘要： Thermal interface compositions (20) contain filler particles possessing a maximum particle size less than 25 microns in diameter blended with a polymer matrix. Such compositions enable lower attainable bond line thickness, which decreases in-situ thermal resistances that exist between thermal interface materials (20) and the corresponding mating surfaces.
摘要翻译：热界面组合物（20）含有直径与聚合物基质共混的直径小于25微米的填料颗粒。这种组合物使得可获得的可获得的粘合线厚度降低，这降低了存在于热界面材料（20）和相应配合表面之间的原位热阻。

24. 发明申请

US20050186788A1 System for improving thermal stability of copper damascene structure 审中-公开
公开(公告)号：US20050186788A1
公开(公告)日：2005-08-25
申请号：US11090103
申请日：2005-03-24
申请人： Jiong-Ping Lu , Qi-Zhong Hong , Tz-Cheng Chiu , Changming Jin , David Permana , Ting Tsui
发明人： Jiong-Ping Lu , Qi-Zhong Hong , Tz-Cheng Chiu , Changming Jin , David Permana , Ting Tsui
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76877 , H01L21/76883
摘要： Disclosed is a system for fabricating a semiconductor device (100). An interconnect structure (110) is formed on the semiconductor device (100) and a cap (112) is deposited over the interconnect structure (110). The interconnect structure (110) is annealed with the overlying cap (112) in place. The cap (112) is then removed after the interconnect structure (110) is annealed.

25. 发明授权

US06835648B2 Semiconductor PMD layer dielectric 有权
标题翻译：半导体PMD层电介质
公开(公告)号：US06835648B2
公开(公告)日：2004-12-28
申请号：US10448097
申请日：2003-05-29
申请人： Qi-Zhong Hong , Peter Huang
发明人： Qi-Zhong Hong , Peter Huang
IPC分类号： H01L214763
CPC分类号： H01L23/3192 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention is a method of manufacturing a semiconductor wafer 2 where a layer of undoped silicon glass 15 is formed over the front-end structure 3. Another embodiment of the present invention is an integrated circuit 2 having a back-end structure 4 in which the dielectric layer 15 contains undoped silicon glass.
摘要翻译：本发明的实施例是制造半导体晶片2的方法，其中在前端结构3上形成未掺杂的硅玻璃15层。本发明的另一个实施例是具有后端结构4的集成电路2 其中介电层15包含未掺杂的硅玻璃。

26. 发明授权

US06544886B2 Process for isolating an exposed conducting surface 有权
公开(公告)号：US06544886B2
公开(公告)日：2003-04-08
申请号：US09574731
申请日：2000-05-18
申请人： Jiong-Ping Lu , Qi-Zhong Hong , Duane E. Carter , Yung Liu
发明人： Jiong-Ping Lu , Qi-Zhong Hong , Duane E. Carter , Yung Liu
IPC分类号： H01L214763
CPC分类号： H01L21/02244 , H01L21/02178 , H01L21/02252 , H01L21/02255 , H01L21/28562 , H01L21/31683 , H01L21/76831 , H01L21/76834 , H01L21/76888
摘要： A method of isolating an exposed conductive surface. An aluminum layer (130) is selectively formed over the exposed conductive (106) surface (e.g., Cu) but not over the surrounding dielectric (110) surface using a thermal CVD process. The aluminum layer (130) is then oxidized to form a thin isolating aluminum-oxide (108) over only the conductive surface. The isolating aluminum-oxide provides a barrier for the Cu while taking up minimal space and reducing the effective dielectric constant.

27. 发明授权

US06461955B1 Yield improvement of dual damascene fabrication through oxide filling 有权
标题翻译：通过氧化物填充的双镶嵌制造的产量提高
公开(公告)号：US06461955B1
公开(公告)日：2002-10-08
申请号：US09521325
申请日：2000-03-09
申请人： Robert Tsu , Qi-Zhong Hong , William R. Mckee
发明人： Robert Tsu , Qi-Zhong Hong , William R. Mckee
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/76805
摘要： A dual damascene process. After the via etch, a via protect layer (114) is deposited in the via (112). The via protect layer (114) comprises a material that has a dry etch rate at least equal to that of the IMD (108) and a wet etch rate that is approximately 100 times that of the IMD (108) or greater. Exemplary materials include PSG, BPSG, and HSQ. The trench pattern (120) is formed and both the via protect layer (114) and IMD (108) are etched. The remaining portions of the via protect layer (114) are then removed prior to forming the metal layer (122).
摘要翻译：双镶嵌工艺。在通孔蚀刻之后，通孔保护层（114）沉积在通孔（112）中。通孔保护层（114）包括具有至少等于IMD（108）的干蚀刻速率的干蚀刻速率和大约为IMD（108）或更大的100倍的湿蚀刻速率的材料。示例性材料包括PSG，BPSG和HSQ。形成沟槽图案（120）并蚀刻通孔保护层（114）和IMD（108）。然后在形成金属层（122）之前去除通孔保护层（114）的剩余部分。

28. 发明授权

US06372566B1 Method of forming a silicide layer using metallic impurities and pre-amorphization 失效
标题翻译：使用金属杂质形成硅化物层和预非晶化的方法
公开(公告)号：US06372566B1
公开(公告)日：2002-04-16
申请号：US09110034
申请日：1998-07-02
申请人： Jorge A. Kittl , Qi-Zhong Hong
发明人： Jorge A. Kittl , Qi-Zhong Hong
IPC分类号： H01L218238
CPC分类号： H01L21/28052 , H01L21/26506 , H01L21/26513 , H01L21/28518 , H01L29/665
摘要： An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming a conductive structure insulatively disposed over the semiconductor substrate (step 302 of FIG. 3); introducing a silicide enhancing substance into the conductive structure (step 304 of FIG. 3); amorphizing a portion of the conductive structure; forming a metal layer on the conductive structure (step 310 of FIG. 3); and wherein the metal layer interacts with the silicide enhancing substance in the amorphized portion of the conductive structure so as to form a lower resistivity silicide on the conductive structure. The conductive structure is, preferably, comprised of: doped polysilicon, undoped polysilicon, epitaxial silicon, or any combination thereof. Preferably, the silicide enhancing substance is comprised of: molybdenum, Co, W, Ta, Nb, Ru, Cr, any refractory metal, and any combination thereof. The metal layer is, preferably, comprised of: titanium, Co, W, Mo, nickel, platinum, palladium, and any combination thereof.
摘要翻译：本发明的一个实施例是制造具有绝缘地设置在半导体衬底上的硅化栅结构的晶体管的方法，该方法包括以下步骤：形成绝缘地设置在半导体衬底上的导电结构（图3的步骤302） ; 将硅化物增强物质引入导电结构体（图3的步骤304）; 导电结构的一部分非晶化; 在导电结构上形成金属层（图3的步骤310）; 并且其中所述金属层与所述导电结构的非晶化部分中的所述硅化物增强物质相互作用，以便在所述导电结构上形成较低电阻率的硅化物。导电结构优选地包括：掺杂多晶硅，未掺杂多晶硅，外延硅或其任何组合。优选地，硅化物增强物质包括：钼，钴，钨，钽，铌，钌，铬，任何难熔金属及其任何组合。金属层优选由钛，钴，钨，钼，镍，铂，钯及其任何组合组成。

29. 发明授权

US06245672B1 Method of forming diffusion barriers for copper metallization in integrated cirucits 有权
标题翻译：在集成的铁芯中形成铜金属化的扩散阻挡层的方法
公开(公告)号：US06245672B1
公开(公告)日：2001-06-12
申请号：US09177412
申请日：1998-10-23
申请人： Qi-Zhong Hong , Wei-Yung Hsu , Jiong-Ping Lu , Robert H. Havemann
发明人： Qi-Zhong Hong , Wei-Yung Hsu , Jiong-Ping Lu , Robert H. Havemann
IPC分类号： H01L214763
CPC分类号： H01L21/76856 , H01L21/76843 , H01L21/76855
摘要： An integrated circuit structure including copper metallization (20, 32, 42), and a method of fabricating the same are disclosed. The structure includes a doped region (7) of a silicon substrate (9), which is typically clad with a metal silicide film (12) formed by way of direct react silicidation. At contact locations (CT) at which the copper metallization (20, 32, 42) is to make contact to the doped region (7), a chemically-densified barrier layer (16, 30, 38) provides a diffusion barrier to the overlying copper metallization (20, 32, 42). The chemically-densified barrier layer (16, 30, 38) is formed by an anneal of the structure to react impurities (14, 28, 36) with the underlying refractory-metal-based film (12, 34); the impurities are introduced by way of wet chemistry, plasma bombardment, or from the ambient in which the structure is annealed.
摘要翻译：公开了一种包括铜金属化（20,32,42）的集成电路结构及其制造方法。该结构包括硅衬底（9）的掺杂区域（7），其通常用通过直接反应硅化形成的金属硅化物膜（12）包覆。在铜金属化层（20,32,42）将与掺杂区域（7）接触的接触位置（CT）处，化学致密化的势垒层（16,30,38）为覆盖层铜金属化（20,32,42）。化学致密化的阻挡层（16,30,38）通过该结构的退火形成，以使杂质（14,28,36）与下面的耐熔金属基膜（12,34）反应; 杂质通过湿化学，等离子体轰击或结构退火的环境引入。

30. 发明授权

US6150252A Multi-stage semiconductor cavity filling process 失效
标题翻译：多级半导体腔填充工艺
公开(公告)号：US6150252A
公开(公告)日：2000-11-21
申请号：US654810
申请日：1996-05-29
申请人： Wei-Yung Hsu , Qi-Zhong Hong
发明人： Wei-Yung Hsu , Qi-Zhong Hong
IPC分类号： H01L21/283 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76858 , H01L21/76843 , H01L21/76877
摘要： Cavities such as vias and contacts formed in semiconductor devices are filled in a multi-stage process to provide low resistance electrical connections. A liner is first deposited into the cavity at a relatively low power and deposition rate to enhance "wetting" of a subsequently deposited fill material. The fill material is deposited at a comparatively greater power and deposition rate to close the mouth of the cavity, after which the fill material is extruded at high pressure into the cavity to substantially fill the cavity. Relatively low processing temperatures and high pressures are utilized to allow for the use of lower dielectric constant dielectrics, which are thermally unstable at conventional processing temperatures.
摘要翻译：诸如在半导体器件中形成的通孔和触点的腔被填充在多级工艺中以提供低电阻电连接。首先以相对低的功率和沉积速率将衬垫沉积到腔中，以增强随后沉积的填充材料的“润湿”。填充材料以相对较大的功率和沉积速率沉积以封闭空腔的口部，然后将填充材料以高压挤出到空腔中以基本上填充空腔。使用相对低的加工温度和高压力来允许使用在常规加工温度下热不稳定的较低介电常数电介质。

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