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21. 发明申请

US20060148188A1 Fabrication method for bipolar integrated circuits 审中-公开
标题翻译：双极集成电路制造方法
公开(公告)号：US20060148188A1
公开(公告)日：2006-07-06
申请号：US11028666
申请日：2005-01-05
申请人： Xian Liu , Chong Ren , Bin Qiu , Xu Xu
发明人： Xian Liu , Chong Ren , Bin Qiu , Xu Xu
IPC分类号： H01L21/8222
CPC分类号： H01L27/0658
摘要： A fabrication method is applied to the bipolar integrated circuit, which combines with various patterns of the masks using in the different processes to form a combination mask. By using the combination mask, a silicon dioxide layer is etched to produce the open windows required in the different processes. Thereafter, according to the requirements of different processes, the unused windows are covered with photoresists to avoid the alignment errors resulted from the pattering and etching of different masks. Because the method doesn't need to reserve tolerance for alignment errors, the degree of integration of the semiconductor processes is enhanced and the cost of production is reduced.
摘要翻译：一种制造方法应用于双极集成电路，其结合了在不同工艺中使用的掩模的各种图案以形成组合掩模。通过使用组合掩模，蚀刻二氧化硅层以产生不同工艺中所需的开放窗口。此后，根据不同过程的要求，未使用的窗口被光致抗蚀剂覆盖，以避免不同掩模的图案和蚀刻产生的对准误差。由于该方法不需要对准误差的预留容差，所以提高了半导体工艺的集成度，降低了生产成本。

22. 发明申请

US20060043528A1 Lateral PNP transistor and the method of manufacturing the same 审中-公开
标题翻译：横向PNP晶体管及其制造方法
公开(公告)号：US20060043528A1
公开(公告)日：2006-03-02
申请号：US10930851
申请日：2004-09-01
申请人： Chong Ren , Xian Liu , Bin Qiu
发明人： Chong Ren , Xian Liu , Bin Qiu
IPC分类号： H01L27/082
CPC分类号： H01L29/6625 , H01L21/8249 , H01L29/735
摘要： The present invention relates to a lateral PNP transistor and the method of manufacturing the same. The medium doping N-type base area and the light doping P− collector area were first introduced in the structure before the formation of P+ doping emitter area and the collector area. The emitter-base-collector doping profile in the lateral and the base width of LPNP were similar to NPN. The designer can optimize the doping profile and area size of each area according to the request of the current gain (Hfe), collector-base breakdown voltage (BVceo), and Early voltage (VA) of LPNP transistor. These advantages may cause to reduce the area and enhance performance of the LPNP transistor.
摘要翻译：本发明涉及一种横向PNP晶体管及其制造方法。在掺杂发射极区域和集电极区域形成之前，首先引入介质掺杂的N型基极区域和掺杂光的P 集电极区域。 LPNP的横向和底部宽度的发射极 - 基极 - 集电极掺杂分布类似于NPN。根据当前增益（Hfe），集电极基极击穿电压（BVceo）和LPNP晶体管的早期电压（VA）的要求，设计人员可以优化各个区域的掺杂特性和面积。这些优点可能导致LPNP晶体管的面积减小和性能的提高。

23. 发明授权

US06409529B1 SIM card connector with improved grounding pin 失效
标题翻译： SIM卡连接器带有改进的接地引脚
公开(公告)号：US06409529B1
公开(公告)日：2002-06-25
申请号：US09875626
申请日：2001-06-05
申请人： Jun Xian Liu , Shaoping Du , Jian Qiang Zhang
发明人： Jun Xian Liu , Shaoping Du , Jian Qiang Zhang
IPC分类号： H01R2900
CPC分类号： H01R13/2442
摘要： A Subscriber Identity Module connector (1) includes an insulative housing (10) having a front and a rear rows of recesses (11), a plurality of terminals (20) retained in the recesses with contact portions (21) extending beyond a top surface of the housing for being horizontally exerted on by a SIM card (40), and a grounding pin (30) retained in a front portion of the recess of the rear row with a transitional portion (311) extending upwardly and forwardly beyond the top surface of the housing for being horizontally exerted on by the SIM card. During insertion, a SIM card slides on the grounding pin and exerts horizontal force on the transitional portion of the grounding pin to form the working circuit after the contact pads of the card fully engage with the contact portions of the terminals.
摘要翻译：订户身份模块连接器（1）包括具有前排和后排凹口（11）的绝缘壳体（10），多个端子（20），其保持在凹部中，接触部分（21）延伸超过顶表面通过SIM卡（40）水平地施加在外壳上的接地销（30），以及保持在后排的凹部的前部的接地销（30），其具有向上并向前延伸超过顶表面的过渡部分（311）的壳体被水平地施加在SIM卡上。在插入时，SIM卡在接地引脚上滑动，并在接地引脚的过渡部分施加水平力，以在卡的接触垫与端子的接触部分完全接合之后形成工作电路。

24. 发明授权

US08578369B2 Managing memory in multiple virtual machines 有权
标题翻译：管理多个虚拟机中的内存
公开(公告)号：US08578369B2
公开(公告)日：2013-11-05
申请号：US13330769
申请日：2011-12-20
申请人： Xiao Jun Dai , Zhi Gan , Rui Bo Han , Xian Liu
发明人： Xiao Jun Dai , Zhi Gan , Rui Bo Han , Xian Liu
IPC分类号： G06F9/46 , G06F9/44 , G06F9/445
CPC分类号： G06F9/45558 , G06F9/5077 , G06F2009/45583
摘要： Virtual machines are managed by obtaining software hierarchy information of a current virtual machine to be installed. Then logical memory assigned to the current virtual machine is divided into a private part and a shared part based at least in part upon existing software hierarchy information of at least one virtual machine already installed and the software hierarchy information of the current virtual machine. Then, the shared part of the logical memory is mapped to shared segments of a physical memory, wherein the shared segments are used by at least one installed virtual machine.
摘要翻译：通过获取要安装的当前虚拟机的软件层次结构信息来管理虚拟机。然后，至少部分地基于已经安装的至少一个虚拟机的现有软件层级信息和当前虚拟机的软件层级信息，分配给当前虚拟机的逻辑存储器被分为私有部分和共享部分。然后，逻辑存储器的共享部分被映射到物理存储器的共享段，其中共享段由至少一个安装的虚拟机使用。

25. 发明申请

US20130234223A1 Self-Aligned Stack Gate Structure For Use In A Non-volatile Memory Array And A Method Of Forming Such Structure 有权
标题翻译：用于非易失性存储器阵列的自对准堆栈门结构和形成这种结构的方法
公开(公告)号：US20130234223A1
公开(公告)日：2013-09-12
申请号：US13414400
申请日：2012-03-07
申请人： Willem-Jan Toren , Xian Liu , Gerhard Metzger-Brueckl , Nhan Do , Stephan Wege , Nadia Miridi , Chien-Sheng Su , Cecile Bernardi , Liz Cuevas , Florence Guyot , Yueh-Hsin Chen , Henry Om'mani , Mandana Tadayoni
发明人： Willem-Jan Toren , Xian Liu , Gerhard Metzger-Brueckl , Nhan Do , Stephan Wege , Nadia Miridi , Chien-Sheng Su , Cecile Bernardi , Liz Cuevas , Florence Guyot , Yueh-Hsin Chen , Henry Om'mani , Mandana Tadayoni
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L29/66545 , H01L21/28273 , H01L21/28282 , H01L21/76283 , H01L27/11521 , H01L27/11568
摘要： A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.
摘要翻译：用于非易失性存储器阵列的堆叠栅极结构具有半导体衬底，该半导体衬底具有多个基本上平行的间隔开的有源区，每个有源区具有沿第一方向的轴。在垂直于第一方向的第二方向上，第一绝缘材料位于每个堆叠栅极结构之间。每个堆叠栅极结构在有源区域上具有第二绝缘材料，在第二绝缘材料上方的电荷保持栅极，电荷保持栅极上方的第三绝缘材料以及位于第三绝缘材料上的控制栅极的第一部分。控制栅极的第二部分在控制栅极的第一部分之上，并且与第一部分相邻并且在第二方向上延伸。第四绝缘材料位于控制栅极的第二部分之上。

26. 发明授权

US07868375B2 Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing 有权
公开(公告)号：US07868375B2
公开(公告)日：2011-01-11
申请号：US12618632
申请日：2009-11-13
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien Sheng Su , Yaw Wen Hu
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

27. 发明申请

US20070218716A1 Contacts of board-to-board connector 有权
标题翻译：板对板连接器的触点
公开(公告)号：US20070218716A1
公开(公告)日：2007-09-20
申请号：US11803964
申请日：2007-05-16
申请人： Jun-Xian Liu
发明人： Jun-Xian Liu
IPC分类号： H01R12/00
CPC分类号： H01R13/26 , H01R12/52 , H01R12/716
摘要： An electrical connector assembly includes a socket connector soldered on one circuit board and a plug connector soldered on another circuit board. The socket connector includes an insulating socket base and a plurality of first terminals received in the first terminal-receiving slots of the insulating socket base. Each first terminal successively extends to form a first terminal lead, a first inverted U-shaped portion, a base U-shaped portion and an auxiliary-clamping portion. One leg of the base U-shaped portion includes a first elastic-contact portion. The plug connector includes an insulating plug base and a plurality of second terminals received in the second terminal-receiving slots of the insulating plug base. Each second terminal successively extends to form a second terminal lead and a second inverted U-shaped portion having a second elastic-contact portion. The second inverted U-shaped portion of the second terminal is inserted into the base U-shaped portion of the first terminal, and the first elastic-contact portion contacts the second elastic-contact portion when mating. The invention can provide stable mating and electrical connection and is in compliance with recent downsizing trends.
摘要翻译：电连接器组件包括焊接在一个电路板上的插座连接器和焊接在另一个电路板上的插头连接器。插座连接器包括绝缘插座底座和容纳在绝缘插座底座的第一端子接收槽中的多个第一端子。每个第一端子依次延伸以形成第一端子引线，第一倒U形部分，基部U形部分和辅助夹紧部分。基部U形部分的一条腿包括第一弹性接触部分。插头连接器包括绝缘插头基座和容纳在绝缘插头基座的第二端子接收槽中的多个第二端子。每个第二端子依次延伸以形成具有第二弹性接触部分的第二端子引线和第二倒U形部分。第二端子的第二倒U形部分被插入到第一端子的基部U形部分中，并且第一弹性接触部分在配合时接触第二弹性接触部分。本发明可以提供稳定的配合和电连接，符合最近的缩小趋势。

28. 发明授权

US08785307B2 Method of forming a memory cell by reducing diffusion of dopants under a gate 有权
标题翻译：通过减少栅极下掺杂剂的扩散形成存储单元的方法
公开(公告)号：US08785307B2
公开(公告)日：2014-07-22
申请号：US13593448
申请日：2012-08-23
申请人： Xian Liu , Mandana Tadayoni , Chien-Sheng Su , Nhan Do
发明人： Xian Liu , Mandana Tadayoni , Chien-Sheng Su , Nhan Do
IPC分类号： H01L21/04
CPC分类号： H01L27/11521 , H01L21/26586 , H01L21/28273 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.
摘要翻译：形成存储单元的方法包括在衬底上形成导电浮栅，在浮置栅极上形成导电控制栅极，在浮栅的一侧横向形成导电擦除栅极，并横向形成导电选择栅极一侧的浮动门。在形成浮置和选择栅极之后，该方法包括使用注入工艺将掺杂剂注入到选择栅极下方的沟道区域的一部分中，所述注入工艺以相对于衬底表面小于九十度，大于零度。

29. 发明授权

US08780639B2 Non-volatile memory device with plural reference cells, and method of setting the reference cells 有权
标题翻译：具有多个参考单元的非易失性存储器件，以及设置参考单元的方法
公开(公告)号：US08780639B2
公开(公告)日：2014-07-15
申请号：US13466878
申请日：2012-05-08
申请人： Xian Liu , Michael James Heinz , Eugene Jinglun Tam , Michael K. Doan , Alexander Kotov , Tho Ngoc Dang , Jack Edward Frayer , Jung Hee Yun , Thuan T. Vu
发明人： Xian Liu , Michael James Heinz , Eugene Jinglun Tam , Michael K. Doan , Alexander Kotov , Tho Ngoc Dang , Jack Edward Frayer , Jung Hee Yun , Thuan T. Vu
IPC分类号： G11C16/06
CPC分类号： G11C7/00 , G11C7/14 , G11C11/5628 , G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.
摘要翻译：非易失性存储器件具有非易失性存储器单元的阵列，第一多个非易失性存储器参考单元，每个参考单元能够被编程到与其它参考单元不同的参考电平; 和第二多个比较器。每个比较器可从第一组非易失性存储器参考单元中的一个连接到非易失性存储器单元阵列中的第三多个存储器单元中的一个。

30. 发明申请

US20140057422A1 Method Of Forming A Memory Cell By Reducing Diffusion Of Dopants Under A Gate 有权
标题翻译：通过减少门下掺杂剂的扩散形成存储单元的方法
公开(公告)号：US20140057422A1
公开(公告)日：2014-02-27
申请号：US13593448
申请日：2012-08-23
申请人： XIAN LIU , MANDANA TADAYONI , CHIEN-SHENG SU , NHAN DO
发明人： XIAN LIU , MANDANA TADAYONI , CHIEN-SHENG SU , NHAN DO
IPC分类号： H01L21/04
CPC分类号： H01L27/11521 , H01L21/26586 , H01L21/28273 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.
摘要翻译：形成存储单元的方法包括在衬底上形成导电浮栅，在浮置栅极上形成导电控制栅极，在浮栅的一侧横向形成导电擦除栅极，并横向形成导电选择栅极一侧的浮动门。在形成浮置和选择栅极之后，该方法包括使用注入工艺将掺杂剂注入到选择栅极下方的沟道区域的一部分中，所述注入工艺以相对于衬底表面小于九十度，大于零度。

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