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21. 发明申请

US20070189093A1 HIGH PERFORMANCE SENSE AMPLIFIER AND METHOD THEREOF FOR MEMORY SYSTEM 有权
标题翻译：高性能感测放大器及其存储系统的方法
公开(公告)号：US20070189093A1
公开(公告)日：2007-08-16
申请号：US11623894
申请日：2007-01-17
申请人： Wenzhe Luo , Paul Ouyang
发明人： Wenzhe Luo , Paul Ouyang
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/062 , G11C16/28
摘要： A system and method for sensing a current. The system includes an operational amplifier including a first input terminal, a second input terminal, and a first output terminal. The first input terminal is biased to a predetermined voltage, and the second input terminal and the first output terminal are directly connected. Additionally, the system includes a switch coupled to the first output terminal and a first node. The switch is controlled by at least a first control signal. Moreover, the system includes a comparator including a third input terminal, a fourth input terminal, and at least a second output terminal. The comparator is configured to receive a first input signal at the third input terminal and a second input signal at the fourth input terminal. The first input signal and the second input signal are associated with the first node and the predetermined voltage.
摘要翻译：一种用于感测电流的系统和方法。该系统包括运算放大器，包括第一输入端，第二输入端和第一输出端。第一输入端被偏压到预定电压，第二输入端和第一输出端直接连接。另外，该系统包括耦合到第一输出端子和第一节点的开关。开关由至少第一控制信号控制。此外，该系统包括比较器，该比较器包括第三输入端，第四输入端和至少第二输出端。比较器被配置为在第三输入端接收第一输入信号，并在第四输入端接收第二输入信号。第一输入信号和第二输入信号与第一节点和预定电压相关联。

22. 发明申请

US20070176672A1 DEVICE AND METHOD FOR VOLTAGE REGULATOR WITH STABLE AND FAST RESPONSE AND LOW STANDBY CURRENT 有权
标题翻译：具有稳定和快速响应和低待机电流的电压调节器的器件和方法
公开(公告)号：US20070176672A1
公开(公告)日：2007-08-02
申请号：US11567135
申请日：2006-12-05
申请人： Wenzhe Luo
发明人： Wenzhe Luo
IPC分类号： G05F1/10
CPC分类号： G05F1/565 , Y10T307/50
摘要： An apparatus and method for regulating voltage levels. The apparatus includes a first transistor and a second transistor. The first transistor and the second transistor are each coupled to a first current source and a second current source. Additionally, the apparatus includes a third transistor coupled to the second transistor and configured to receive a first voltage from the second transistor, and a fourth transistor configured to receive the first voltage from the second transistor and generate an output voltage. Moreover, the apparatus includes an adaptive system coupled to the fourth transistor. Also, the apparatus includes a delay system coupled to the third transistor and configured to receive a sensing current from the third transistor and generate a delayed current associated with a predetermined time delay. Additionally, the apparatus includes a current generation system.
摘要翻译：一种用于调节电压电平的装置和方法。该装置包括第一晶体管和第二晶体管。第一晶体管和第二晶体管分别耦合到第一电流源和第二电流源。此外，该装置包括耦合到第二晶体管并被配置为从第二晶体管接收第一电压的第三晶体管，以及被配置为从第二晶体管接收第一电压并产生输出电压的第四晶体管。此外，该装置包括耦合到第四晶体管的自适应系统。而且，该装置包括耦合到第三晶体管并被配置为从第三晶体管接收感测电流并产生与预定时间延迟相关联的延迟电流的延迟系统。另外，该装置包括电流发生系统。

23. 发明授权

US07233868B2 System and method for providing adaptive power supply to system on a chip 有权
标题翻译：用于向芯片上的系统提供自适应电源的系统和方法
公开(公告)号：US07233868B2
公开(公告)日：2007-06-19
申请号：US11251583
申请日：2005-10-13
申请人： Wenzhe Luo , Paul Ouyang , Feng Chen
发明人： Wenzhe Luo , Paul Ouyang , Feng Chen
IPC分类号： G01R19/00 , G01R35/04
CPC分类号： G06F1/26 , Y10T307/305 , Y10T307/383 , Y10T307/50
摘要： A system and method for adaptively providing a power supply voltage. The system includes an input/output subsystem configured to receive a first voltage, an analog subsystem configured to receive a second voltage and coupled to the input/output subsystem, a first digital subsystem configured to receive a third voltage and coupled to the input/output subsystem, and a second digital subsystem configured to receive a fourth voltage and coupled to the input/output subsystem, the first digital subsystem, and the analog subsystem. Additionally, the system includes a first adaptive power supply configured to receive an input voltage and generate the third voltage, and a second adaptive power supply configured to receive the input voltage and generate the fourth voltage.
摘要翻译：一种用于自适应地提供电源电压的系统和方法。该系统包括被配置为接收第一电压的输入/输出子系统，被配置为接收第二电压并耦合到输入/输出子系统的模拟子系统，被配置为接收第三电压并耦合到输入/输出的第一数字子系统子系统和被配置为接收第四电压并耦合到输入/输出子系统，第一数字子系统和模拟子系统的第二数字子系统。另外，该系统包括被配置为接收输入电压并产生第三电压的第一自适应电源，以及被配置为接收输入电压并产生第四电压的第二自适应电源。

24. 发明申请

US20070058084A1 System and method for adaptive power supply to reduce power consumption 有权
标题翻译：自适应电源的系统和方法，以降低功耗
公开(公告)号：US20070058084A1
公开(公告)日：2007-03-15
申请号：US11251107
申请日：2005-10-13
申请人： Wenzhe Luo , Paul Ouyang , Feng Chen
发明人： Wenzhe Luo , Paul Ouyang , Feng Chen
IPC分类号： H04N5/63
CPC分类号： H02M3/07
摘要： A system and method for adaptively providing a power supply voltage. The system includes an oscillator configured to receive an output voltage and generate a firs signal. The first signal is associated with a first frequency and a first period. Additionally, the system includes a frequency comparator configured to receive the first signal associated with the first frequency and a second signal associated with a second frequency and to generate a third signal if the first frequency and the second frequency are not equal, and a voltage regulator coupled to the frequency comparator and configured to generate the output voltage based on at least information associated with the third signal. The output voltage is received by a powered system, and the powered system is configured to receive a clock signal associated with a clock frequency. The clock frequency is equal to the second frequency.
摘要翻译：一种用于自适应地提供电源电压的系统和方法。该系统包括被配置为接收输出电压并产生第一信号的振荡器。第一信号与第一频率和第一周期相关联。另外，该系统包括：频率比较器，被配置为接收与第一频率相关联的第一信号和与第二频率相关联的第二信号，并且如果第一频率和第二频率不相等则产生第三信号;以及电压调节器耦合到频率比较器并被配置为基于至少与第三信号相关联的信息来产生输出电压。输出电压由供电系统接收，并且供电系统被配置为接收与时钟频率相关联的时钟信号。时钟频率等于第二个频率。

25. 发明授权

US07190189B2 Device and method for voltage regulator with stable and fast response and low standby current 有权
标题翻译：电压调节器的装置和方法，响应平稳，待机电流低
公开(公告)号：US07190189B2
公开(公告)日：2007-03-13
申请号：US11060922
申请日：2005-02-17
申请人： Wenzhe Luo
发明人： Wenzhe Luo
IPC分类号： H03K17/16
CPC分类号： G05F1/565 , Y10T307/50
摘要： An apparatus and method for regulating voltage levels. The apparatus includes a first transistor and a second transistor. The first transistor and the second transistor are each coupled to a first current source and a second current source. Additionally, the apparatus includes a third transistor coupled to the second transistor and configured to receive a first voltage from the second transistor, and a fourth transistor configured to receive the first voltage from the second transistor and generate an output voltage. Moreover, the apparatus includes an adaptive system coupled to the fourth transistor. Also, the apparatus includes a delay system coupled to the third transistor and configured to receive a sensing current from the third transistor and generate a delayed current associated with a predetermined time delay. Additionally, the apparatus includes a current generation system.
摘要翻译：一种用于调节电压电平的装置和方法。该装置包括第一晶体管和第二晶体管。第一晶体管和第二晶体管分别耦合到第一电流源和第二电流源。此外，该装置包括耦合到第二晶体管并被配置为从第二晶体管接收第一电压的第三晶体管，以及被配置为从第二晶体管接收第一电压并产生输出电压的第四晶体管。此外，该装置包括耦合到第四晶体管的自适应系统。而且，该装置包括耦合到第三晶体管并被配置为从第三晶体管接收感测电流并产生与预定时间延迟相关联的延迟电流的延迟系统。另外，该装置包括电流发生系统。

26. 发明授权

US06842053B1 Reduced charge injection in current switch 失效
标题翻译：减少电流开关中的电荷注入
公开(公告)号：US06842053B1
公开(公告)日：2005-01-11
申请号：US09188241
申请日：1998-11-09
申请人： Wenzhe Luo
发明人： Wenzhe Luo
IPC分类号： H03K17/041 , H03K17/16
CPC分类号： H03K17/162 , H03K17/04106
摘要： A current switching circuit has greatly reduced charge injection effects with the introduction of a mirror path to mirror the switch path. The mirror path comprises a complementary switch and a pulling amplifier, e.g., a pull-down amplifier for a source current switching circuit, or a pull-up amplifier for a sink current switch circuit. The pulling amplifier mirrors the status of an output path of a current source, e.g., a transistor current source, such that when the current source is switched ON or OFF, the switching process with respect to the load, e.g., a load capacitor, is smooth and provides a clean current waveform due to greatly reduced charge injection.
摘要翻译：电流开关电路通过引入镜像路径来反映开关路径，大大降低了电荷注入效果。镜面路径包括互补开关和拉动放大器，例如用于源极电流切换电路的下拉放大器或用于吸收电流开关电路的上拉放大器。拉动放大器反映电流源（例如，晶体管电流源）的输出路径的状态，使得当电流源被接通或断开时，相对于负载的开关过程（例如负载电容器）是平滑，并提供清洁的电流波形，由于大大减少了电荷注入。

27. 发明授权

US06266780B1 Glitchless clock switch 有权
标题翻译：无毛刺时钟切换
公开(公告)号：US06266780B1
公开(公告)日：2001-07-24
申请号：US09219799
申请日：1998-12-23
申请人： Jeffrey Paul Grundvig , Wenzhe Luo , Zhigang Ma , Brian John Petryna
发明人： Jeffrey Paul Grundvig , Wenzhe Luo , Zhigang Ma , Brian John Petryna
IPC分类号： G06F112
CPC分类号： G06F1/12
摘要： A glitchless clock switch in accordance with the principles of the present invention avoids the need to directly synchronize clock selection signals with the source clock. Instead, clock switching control signals are generated with relation to Finite-State-Machines (FSMs) for each clock signal. Thus, the cycle relationship of the different clock sources do not affect the clock switching process. The FSM for each clock has three states: ON, STOP, and IDLE. During the switching process, each clock signal enters its respective IDLE state. Detection of the ALL_IDLE state is synchronized with a directly derived signal from the newly selected clock. Any glitches in the switching process are isolated to the control of the synchronization of the ALL_IDLE state, which does not affect the output clock signal.
摘要翻译：根据本发明的原理的无毛刺时钟切换避免了将时钟选择信号与源时钟直接同步的需要。相反，与每个时钟信号的有限状态机（FSM）相关地生成时钟切换控制信号。因此，不同时钟源的周期关系不会影响时钟切换过程。每个时钟的FSM有三种状态：ON，STOP和IDLE。在切换过程中，每个时钟信号进入其相应的空闲状态。 ALL_IDLE状态的检测与来自新选择的时钟的直接导出信号同步。切换过程中的任何毛刺都被隔离，以控制ALL_IDLE状态的同步，这不影响输出时钟信号。

28. 发明授权

US6091627A Message box memory cell for two-side asynchronous access 有权
标题翻译：用于双向异步访问的消息框存储单元
公开(公告)号：US6091627A
公开(公告)日：2000-07-18
申请号：US154276
申请日：1998-09-16
申请人： Wenzhe Luo , Brian J. Petryna
发明人： Wenzhe Luo , Brian J. Petryna
IPC分类号： G11C8/16 , G11C7/00
CPC分类号： G11C8/16
摘要： A new memory cell design having differential and dedicated read and write ports is disclosed. The memory cell utilizes separate write and read bit lines. The read bit lines are pre-charged to a first level. A grounding transistor is provided between the circuitry containing the cell's contents and the read bit lines such that the contents of the cell are isolated from the read bit lines. The grounding transistor is activated and deactivated by the data within the cell. The activation and deactivation of the grounding transistor causes the pre-charged bit lines to be pulled-down to a second level or to remain at the first level to accurately reflect the contents of the cell. Since the circuitry containing the contents of the cell is isolated from the read bit lines, a read operation on the cell will not interfere with an in progress write operation and thus, destruction of the cell's contents is prevented. In addition, the isolation prevents bit line coupling.
摘要翻译：公开了一种具有差分和专用读写端口的新型存储单元设计。存储单元利用单独的写和读位线。读取位线被预充电到第一级。在包含单元的内容的电路和读位线之间提供接地晶体管，使得单元的内容与读位线隔离。接地晶体管由单元内的数据激活和去激活。接地晶体管的激活和去激活使得预充电的位线被下拉到第二电平或保持在第一电平以准确地反映电池的内容。由于包含单元的内容的电路与读取的位线隔离，所以对单元的读取操作不会妨碍正在进行的写入操作，因此可以防止单元的内容的破坏。此外，隔离可防止位线耦合。

29. 发明授权

US08320193B2 Method of flash memory design with differential cell for better endurance 有权
标题翻译：具有差分电池的闪存设计方法，以提高耐久性
公开(公告)号：US08320193B2
公开(公告)日：2012-11-27
申请号：US12794697
申请日：2010-06-04
申请人： Wenzhe Luo , Paul Ouyang
发明人： Wenzhe Luo , Paul Ouyang
IPC分类号： G11C11/34
CPC分类号： G11C16/0441 , G11C16/10
摘要： A flash memory system includes a first flash memory cell having a first floating gate, a first source region, and a first control gate. The first control gate is connected to a word line. The first flash memory cell includes a first oxide layer separating the first control gate from the first floating gate and a first drain region connecting to a first bit line. The flash memory system also includes a second flash memory cell having a second floating gate, a second source region, and a second control gate. The second control gate is connected to the word line. The second flash memory cell includes a second oxide layer separating the second control gate from the second floating gate and a second drain region connecting to a second bit line. A comparator processes a first and second input signals received from the respective first and second bit lines.
摘要翻译：闪存系统包括具有第一浮动栅极，第一源极区域和第一控制栅极的第一闪存单元。第一个控制门连接到一个字线。第一闪存单元包括将第一控制栅极与第一浮置栅极分开的第一氧化物层和连接到第一位线的第一漏极区域。闪存系统还包括具有第二浮动栅极，第二源极区域和第二控制栅极的第二闪存单元。第二控制栅极连接到字线。第二闪速存储单元包括将第二控制栅极与第二浮置栅极分离的第二氧化物层和连接到第二位线的第二漏极区域。 A比较器处理从相应的第一和第二位线接收的第一和第二输入信号。

30. 发明授权

US08200280B2 Cordless telephone with digital audio player capability 有权
标题翻译：带数字音频播放器的无绳电话
公开(公告)号：US08200280B2
公开(公告)日：2012-06-12
申请号：US13096420
申请日：2011-04-28
申请人： Qinghong Cao , Liang Jin , Wenzhe Luo , Jian Wu , Zhigang Ma
发明人： Qinghong Cao , Liang Jin , Wenzhe Luo , Jian Wu , Zhigang Ma
IPC分类号： H04M1/00
CPC分类号： H04M1/72558 , H04M1/57 , H04M1/6041 , H04M1/72502 , H04M1/72527
摘要： A cordless telephone which allows a user to play MP3 digital audio bit stream music, using the remote handset of a cordless telephone to control the functions of the MP3 player. The cordless telephone remains usable as a typical cordless telephone with all the features and conveniences of a cordless telephone including, but not limited to, connection of a telephone call between a calling party and a called party, caller ID information, voice messaging features, etc. MP3 digital audio bit stream music may be downloaded from a remote source through, e.g., the Internet and a PC.
摘要翻译：一种无绳电话，允许用户使用无绳电话的远程手机来播放MP3数字音频比特流音乐，以控制MP3播放器的功能。无绳电话保持可用作典型的无绳电话，具有无绳电话的所有特征和便利性，包括但不限于主叫方和被叫方之间的电话呼叫的连接，呼叫者ID信息，语音消息收发特征等 MP3数字音频比特流音乐可以通过例如因特网和PC从远程源下载。

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