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    • 21. 发明授权
    • Memory architecture with enhanced over-erase tolerant control gate scheme
    • 具有增强的过擦除宽容控制门控方案的存储架构
    • US07180779B2
    • 2007-02-20
    • US11178965
    • 2005-07-11
    • Nicola TeleccoVictor Nguyen
    • Nicola TeleccoVictor Nguyen
    • G11C11/34
    • G11C16/3468G11C16/26G11C16/3477
    • The present invention is related to semiconductor memories, and in particular, to a nonvolatile or flash memory and method that reduces the effect of or is tolerant of over-erased memory cells. When a memory cell is read, a read voltage is applied to at least one target memory cell, and a negative bias voltage that is lower than a threshold voltage of an over-erased memory cell is also applied to at least one other selected memory cell that is in the same row as the target memory cell. Applying a negative bias voltage to adjacent or proximate memory cells shuts off nearby cells to isolate current that may come from over-erased memory cells during a read, program, or erase operation.
    • 本发明涉及半导体存储器,特别涉及一种减少过度擦除的存储单元的影响或容忍的非易失性或闪速存储器和方法。 当存储单元被读取时,读取电压被施加到至少一个目标存储单元,并且低于过擦除存储单元的阈值电压的负偏置电压也被施加到至少一个其他选择的存储单元 它与目标存储单元处于同一行。 对相邻或邻近的存储器单元施加负偏置电压会关闭附近的单元,以隔离在读取,编程或擦除操作期间来自过擦除的存储单元的电流。