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21. 发明授权

US08237300B2 Genset power system having multiple modes of operation 有权
标题翻译：发电机组具有多种运行模式
公开(公告)号：US08237300B2
公开(公告)日：2012-08-07
申请号：US12320927
申请日：2009-02-09
申请人： Timothy P. Allen
发明人： Timothy P. Allen
IPC分类号： F02D41/08
CPC分类号： H02J9/08
摘要： A power system is disclosed. The power system may have an engine, a generator, a monitoring device configured to monitor the generator and to generate a signal, and a performance module configured to provide an alarm and a shutdown command to the engine based on the signal. The power system may further have a switching device with a first condition and a second condition. When the first condition of the switching device is active, the performance module may be overridden, the engine may be operated at a reduced speed and load output, and the generator may be inhibited from producing electrical power. When the second condition of the switching device is active, the performance module may affect operation of the power system, the engine may be operated at an elevated speed and load output, and the generator may be allowed to produce electrical power directed to the external load.
摘要翻译：公开了电力系统。电力系统可以具有发动机，发电机，被配置为监视发电机并产生信号的监视装置，以及性能模块，被配置为基于该信号向发动机提供报警和关机命令。电力系统还可以具有具有第一状态和第二状态的开关装置。当开关装置的第一状态为活动时，可以覆盖性能模块，发动机可以以降低的速度和负载输出进行操作，并且可以禁止发电机产生电力。当开关装置的第二状态有效时，性能模块可能会影响电力系统的运行，发动机可以以高速运行和负载输出，并且发电机可以被允许产生指向外部负载的电力。

22. 发明授权

US07822958B1 Booting mechanism for FPGA-based embedded system 有权
标题翻译：基于FPGA的嵌入式系统启动机制
公开(公告)号：US07822958B1
公开(公告)日：2010-10-26
申请号：US11372532
申请日：2006-03-10
申请人： Timothy P. Allen , Andrew Draper , Aaron Ferrucci , Kerry Veenstra
发明人： Timothy P. Allen , Andrew Draper , Aaron Ferrucci , Kerry Veenstra
IPC分类号： G06F9/00 , G06F9/24 , G06F13/00
CPC分类号： G06F9/4401
摘要： According to various embodiments of the present invention, a programmable device assembly includes an FPGA coupled to a nonvolatile serial configuration memory (e.g., serial flash memory) and a volatile fast bulk memory (e.g., SRAM or SDRAM). The nonvolatile serial configuration memory contains both the FPGA configuration data and CPU instructions. When a predetermined condition occurs, a serial memory access component that is hard coded on the FPGA automatically reads the configuration data from the nonvolatile serial configuration memory. The configuration data is used to configure the FPGA with various components, including a CPU, a boot ROM with code for a boot copier, and a bus structure. When the CPU boots, code for the boot copier is executed so that the CPU instructions are copied from the nonvolatile serial configuration memory to the volatile fast bulk memory. The CPU then executes the CPU instructions stored in the volatile fast bulk memory.
摘要翻译：根据本发明的各种实施例，可编程器件组件包括耦合到非易失性串行配置存储器（例如串行闪存）和易失性快速批量存储器（例如，SRAM或SDRAM）的FPGA。非易失性串行配置存储器包含FPGA配置数据和CPU指令。当发生预定条件时，在FPGA上硬编码的串行存储器访问部件自动从非易失性串行配置存储器读取配置数据。配置数据用于配置具有各种组件的FPGA，包括CPU，具有启动复印机代码的引导ROM和总线结构。当CPU引导时，执行引导复印机的代码，以便将CPU指令从非易失性串行配置存储器复制到易失性快速批量存储器。 CPU然后执行存储在易失性快速批量存储器中的CPU指令。

23. 发明授权

US07769934B1 Master and slave side arbitrators associated with programmable chip system components 有权
标题翻译：与可编程芯片系统组件相关的主，从侧仲裁器
公开(公告)号：US07769934B1
公开(公告)日：2010-08-03
申请号：US11759828
申请日：2007-06-07
申请人： Jeffrey Orion Pritchard , Timothy P. Allen
发明人： Jeffrey Orion Pritchard , Timothy P. Allen
IPC分类号： G06F13/00
CPC分类号： G06F13/364 , G06F13/374
摘要： Methods and apparatus are provided for providing a first master component with access to a first slave component while a second master component is accessing a second slave component in a system. The system may include a processor core and peripherals implemented on an integrated circuit. A slave side arbitrator corresponding to a single slave component and coupled to multiple master components can be used to provide a master component access to a slave component.
摘要翻译：提供的方法和装置用于在第二主组件正在访问系统中的第二从组件时提供对第一从组件的访问的第一主组件。该系统可以包括在集成电路上实现的处理器核心和外围设备。可以使用对应于单个从属组件并且耦合到多个主组件的从属侧仲裁器来提供主组件对从组件的访问。

24. 发明申请

US20100156117A1 Genset power system having multiple modes of operation 有权
标题翻译：发电机组具有多种运行模式
公开(公告)号：US20100156117A1
公开(公告)日：2010-06-24
申请号：US12320927
申请日：2009-02-09
申请人： Timothy P. Allen
发明人： Timothy P. Allen
IPC分类号： F02D29/06 , H02P9/04
CPC分类号： H02J9/08
摘要： A power system is disclosed. The power system may have an engine, a generator, a monitoring device configured to monitor the generator and to generate a signal, and a performance module configured to provide an alarm and a shutdown command to the engine based on the signal. The power system may further have a switching device with a first condition and a second condition. When the first condition of the switching device is active, the performance module may be overridden, the engine may be operated at a reduced speed and load output, and the generator may be inhibited from producing electrical power. When the second condition of the switching device is active, the performance module may affect operation of the power system, the engine may be operated at an elevated speed and load output, and the generator may be allowed to produce electrical power directed to the external load.
摘要翻译：公开了电力系统。电力系统可以具有发动机，发电机，被配置为监视发电机并产生信号的监视装置，以及性能模块，被配置为基于该信号向发动机提供报警和关机命令。电力系统还可以具有具有第一状态和第二状态的开关装置。当开关装置的第一状态为活动时，可以覆盖性能模块，发动机可以以降低的速度和负载输出进行操作，并且可以禁止发电机产生电力。当开关装置的第二状态有效时，性能模块可能会影响电力系统的运行，发动机可以以高速运行和负载输出，并且发电机可以被允许产生指向外部负载的电力。

25. 发明授权

US06380931B1 Object position detector with edge motion feature and gesture recognition 有权
标题翻译：具有边缘运动特征和手势识别的物体位置检测器
公开(公告)号：US06380931B1
公开(公告)日：2002-04-30
申请号：US09861070
申请日：2001-05-18
申请人： David W. Gillespie , Timothy P. Allen , Ralph C. Wolf , Shawn P. Day
发明人： David W. Gillespie , Timothy P. Allen , Ralph C. Wolf , Shawn P. Day
IPC分类号： G09G500
CPC分类号： G06F3/04883 , G06F3/03547 , G06F3/041 , G06F3/044 , G06F3/047 , G06F3/0488 , G06F2203/04101 , G06F2203/04808 , G06K9/00335
摘要： Methods for recognizing gestures made by a conductive object on a touch-sensor pad are disclosed. Tapping, pushing, hopping, and zigzag gestures are recognized by analyzing the position, pressure, and movement of the conductive object on the sensor pad during the time of a suspected gesture, and signals are sent to a host indicating the occurrence of these gestures. Signals for compensating for unintended motion of the conductive object on the touch-sensor pad during the gestures are also sent to the host.
摘要翻译：公开了用于识别由触摸传感器垫上的导电物体制成的手势的方法。通过在可疑手势期间分析导电物体在传感器焊盘上的位置，压力和移动来识别攻丝，推动，跳跃和之字形手势，并且将信号发送到指示这些手势的发生的主机。用于在手势期间补偿触摸传感器垫上的导电物体的非预期运动的信号也被发送到主机。

26. 发明授权

US5889236A Pressure sensitive scrollbar feature 失效
标题翻译：压敏滚动条功能
公开(公告)号：US5889236A
公开(公告)日：1999-03-30
申请号：US558114
申请日：1995-11-13
申请人： David Gillespie , Timothy P. Allen , Aaron T. Ferrucci
发明人： David Gillespie , Timothy P. Allen , Aaron T. Ferrucci
IPC分类号： G06F3/023 , G06F3/033 , G06F3/041 , G06F3/044 , G06F3/048 , G08C21/00 , G09G5/08
CPC分类号： G06F3/0488 , G06F3/041 , G06F3/044 , G06F3/04855 , G06F3/04883 , G06F3/04892
摘要： A proximity sensor system includes a sensor matrix array having a characteristic capacitance on horizontal and vertical conductors connected to sensor pads. The capacitance changes as a function of the proximity of an object or objects to the sensor matrix. The change in capacitance of each node in both the X and Y directions of the matrix due to the approach of an object is converted to a set of voltages in the X and Y directions. These voltages are processed by circuitry to develop electrical signals representative of the centroid of the profile of the object, i.e, its position in the X and Y dimensions. Noise reduction and background level setting techniques inherently available in the architecture are employed.
摘要翻译：接近传感器系统包括具有连接到传感器焊盘的水平和垂直导体上的特征电容的传感器矩阵阵列。电容根据物体或传感器矩阵的接近度而变化。由于物体的接近，矩阵的X和Y方向上的每个节点的电容的变化被转换成在X和Y方向上的一组电压。这些电压由电路处理以产生表示物体轮廓的质心的电信号，即其在X和Y尺寸中的位置。采用本构架中固有可用的降噪和背景设置技术。

27. 发明授权

US5880411A Object position detector with edge motion feature and gesture recognition 失效
公开(公告)号：US5880411A
公开(公告)日：1999-03-09
申请号：US623483
申请日：1996-03-28
申请人： David W. Gillespie , Timothy P. Allen , Ralph C. Wolf , Shawn P. Day
发明人： David W. Gillespie , Timothy P. Allen , Ralph C. Wolf , Shawn P. Day
IPC分类号： G06F3/041 , G06F3/033 , G06F3/038 , G06F3/044 , G06F3/047 , G06F3/048 , G06K9/00 , G08C21/00 , G09G5/00 , G09G5/08
CPC分类号： G06F3/04883 , G06F3/03547 , G06F3/041 , G06F3/044 , G06F3/047 , G06F3/0488 , G06K9/00335 , G06F2203/04101 , G06F2203/04808
摘要： Methods for recognizing gestures made by a conductive object on a touch-sensor pad and for cursor motion are disclosed. Tapping, drags, pushes, extended drags and variable drags gestures are recognized by analyzing the position, pressure, and movement of the conductive object on the sensor pad during the time of a suspected gesture, and signals are sent to a host indicating the occurrence of these gestures. Signals indicating the position of a conductive object and distinguishing between the peripheral portion and an inner portion of the touch-sensor pad are also sent to the host.

28. 发明授权

US5629891A Writable analog reference voltage storage device 失效
标题翻译：可写模拟参考电压存储器件
公开(公告)号：US5629891A
公开(公告)日：1997-05-13
申请号：US622763
申请日：1996-03-25
申请人： John LeMoncheck , Timothy P. Allen , Gunter Steinbach , Carver A. Mead
发明人： John LeMoncheck , Timothy P. Allen , Gunter Steinbach , Carver A. Mead
IPC分类号： G05F1/46 , G05F3/24 , G11C5/14 , G11C11/56 , G11C27/00 , B11C16/04
CPC分类号： G05F3/247 , G05F1/468 , G05F3/24 , G11C11/56 , G11C11/5621 , G11C27/005 , G11C5/147 , G11C16/30 , G11C2211/5634 , G11C7/16
摘要： A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Circuitry is provided so that all floating gate storage devices can be programmed to their target voltages individually or in parallel. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A transistor structure with a lightly doped drain is provided for control of the tunneling structure. A capacitor is connected to each floating gate node to provide control of the injection structure. A dynamic analog storage element is provided to store the target voltage for the floating gate storage device. A comparator is provided to monitor the floating gate voltage and target voltage and control tunneling and injection. A digital storage device is provided to statically store the output of the comparator. During normal operation of the voltage reference circuit, the voltage comparator is configured as a follower amplifier to buffer the analog voltage output. During normal operation of the bias reference circuit, the current comparator is configured as a current mirror to buffer the analog current output.
摘要翻译：用于产生用于参考或偏置使用的N个模拟电压信号的电路使用N个模拟浮动栅极存储装置。提供电路，使得所有浮动栅极存储装置可以单独地或并行地编程到它们的目标电压。提供电子注入电路用于将电子注入到上面，并且提供隧道结构用于从每个浮动栅极存储装置的浮动栅极去除电子。提供了具有轻掺杂漏极的晶体管结构，用于控制隧道结构。电容器连接到每个浮动栅极节点以提供对注入结构的控制。提供动态模拟存储元件以存储浮动栅极存储装置的目标电压。提供比较器来监控浮栅电压和目标电压，并控制隧道和注入。提供数字存储设备以静态存储比较器的输出。在电压基准电路正常工作期间，电压比较器被配置为跟随放大器以缓冲模拟电压输出。在偏置参考电路的正常工作期间，电流比较器被配置为电流镜来缓冲模拟电流输出。

29. 发明授权

US5160899A Adaptable MOS current mirror 失效
标题翻译：适应MOS电流镜
公开(公告)号：US5160899A
公开(公告)日：1992-11-03
申请号：US781503
申请日：1991-10-22
申请人： Janeen D. W. Anderson , Carver A. Mead , Timothy P. Allen , Michael F. Wall
发明人： Janeen D. W. Anderson , Carver A. Mead , Timothy P. Allen , Michael F. Wall
IPC分类号： G06N3/063 , H01L27/06 , H03F1/02 , H03F1/30 , H03F3/45
CPC分类号： G06N3/063 , H01L27/0629 , H03F1/0261 , H03F1/303 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： An adaptable current mirror includes first and second MOS transistors. The first MOS transistor has its gate connected to its drain. A MOS capacitor structure is connected in series between the gate of the first MOS transistor and the gate of the second MOS transistor. Electrons may be placed onto and removed in an analog manner from a floating node associated with the second MOS transistor, usually the gate of the transistor, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure. A plurality of adaptable current mirrors communicating with a plurality of current-carrying lines may be employed for indicating the output of the one of the plurality of current-carrying lines through which the most current is flowing.
摘要翻译：适应电流镜包括第一和第二MOS晶体管。第一个MOS晶体管的栅极连接到其漏极。 MOS电容器结构串联连接在第一MOS晶体管的栅极和第二MOS晶体管的栅极之间。电子可以通过施加第一和第二电气控制信号，以模拟方式从与第二MOS晶体管（通常是晶体管的栅极）相关联的浮动节点放置和去除。第一电控信号控制电子从电子注入结构注入到浮动节点上，第二电控信号通过电子去除结构控制从浮动节点去除电子。可以采用与多个载流线路通信的多个适应电流镜，以指示最流动的多个通电线路中的一个的输出。

30. 发明授权

US08412918B1 Booting mechanism for FPGA-based embedded system 有权
标题翻译：基于FPGA的嵌入式系统启动机制
公开(公告)号：US08412918B1
公开(公告)日：2013-04-02
申请号：US12887982
申请日：2010-09-22
申请人： Timothy P. Allen , Andrew Draper , Aaron Ferrucci , Kerry Veenstra
发明人： Timothy P. Allen , Andrew Draper , Aaron Ferrucci , Kerry Veenstra
IPC分类号： G06F9/00 , G06F9/24 , G06F15/177 , G06F12/00
CPC分类号： G06F9/4401
摘要： According to various embodiments, a programmable device assembly includes an FPGA coupled to a nonvolatile serial configuration memory (e.g., serial flash memory) and a volatile fast bulk memory (e.g., SRAM or SDRAM). The nonvolatile serial configuration memory contains both the FPGA configuration data and CPU instructions. When a predetermined condition occurs, a serial memory access component that is hard coded on the FPGA automatically reads the configuration data from the nonvolatile serial configuration memory. The configuration data is used to configure the FPGA with various components, including a CPU, a boot ROM with code for a boot copier, and a bus structure. When the CPU boots, code for the boot copier is executed so that the CPU instructions are copied from the nonvolatile serial configuration memory to the volatile fast bulk memory. The CPU then executes the CPU instructions stored in the volatile fast bulk memory.
摘要翻译：根据各种实施例，可编程设备组件包括耦合到非易失性串行配置存储器（例如，串行闪存）和易失性快速批量存储器（例如，SRAM或SDRAM）的FPGA。非易失性串行配置存储器包含FPGA配置数据和CPU指令。当发生预定条件时，在FPGA上硬编码的串行存储器访问部件自动从非易失性串行配置存储器读取配置数据。配置数据用于配置具有各种组件的FPGA，包括CPU，具有启动复印机代码的引导ROM和总线结构。当CPU引导时，执行引导复印机的代码，以便将CPU指令从非易失性串行配置存储器复制到易失性快速批量存储器。 CPU然后执行存储在易失性快速批量存储器中的CPU指令。

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