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21. 发明授权

US09306596B2 Hybrid CAM assisted deflate decompression accelerator 有权
标题翻译：混合型CAM辅助减压加速器
公开(公告)号：US09306596B2
公开(公告)日：2016-04-05
申请号：US14317698
申请日：2014-06-27
申请人： Sudhir K. Satpathy , Sanu K. Mathew , Vinodh Gopal , Ram K. Krishnamurthy
发明人： Sudhir K. Satpathy , Sanu K. Mathew , Vinodh Gopal , Ram K. Krishnamurthy
IPC分类号： H03M7/30 , H03M7/42 , G06F12/06 , G11C15/00 , G11C15/04
CPC分类号： G06F12/0646 , G06F2212/1021 , G06F2212/401 , G11C15/00 , G11C15/04 , H03M7/3059 , H03M7/3084 , H03M7/3086 , H03M7/40
摘要： Disclosed is an integrated circuit including a memory device including a first portion and a second portion. The first portion is a first type of content addressable memory (CAM) with a first set of cells and the second portion is a second type of CAM with a second set of cells. The first set of cells is smaller than the second set of cells. The integrated circuit further includes a decompression accelerator coupled to the memory device, the decompression accelerator to generate a plurality of length codes. Each of the plurality of length codes include at least one bit. The plurality of length codes are generated using a symbol received from an encoded data stream that includes a plurality of symbols. The decompression accelerator further to store the plurality of length codes in the first portion of the memory device in an order according to their respective number of bits.
摘要翻译：公开了一种集成电路，其包括包括第一部分和第二部分的存储器件。第一部分是具有第一组单元的第一类型的内容可寻址存储器（CAM），并且第二部分是具有第二组单元格的第二类型的CAM。第一组单元格小于第二组单元格。集成电路还包括耦合到存储器件的解压加速器，解压加速器以产生多个长度代码。多个长度码中的每一个包括至少一个位。使用从包括多个符号的编码数据流接收的符号来生成多个长度码。所述解压缩加速器进一步按照它们各自的位数按顺序将所述多个长度代码存储在所述存储器件的第一部分中。

22. 发明申请

US20150280909A1 Instruction and Logic for a Simon Block Cipher 有权
标题翻译：西门子密码的指令和逻辑
公开(公告)号：US20150280909A1
公开(公告)日：2015-10-01
申请号：US14227718
申请日：2014-03-27
申请人： Sanu K. Mathew , Himanshu Kaul , Mark A. Anders
发明人： Sanu K. Mathew , Himanshu Kaul , Mark A. Anders
IPC分类号： H04L9/08 , H04L9/14
CPC分类号： H04L9/0618 , G06F21/62 , G09C1/00 , H04L2209/24
摘要： A processor includes an input-circuit and a Simon block cipher. The Simon block cipher includes a data transformation circuit, a constant generator, and a key expansion circuit. The data transformation circuit includes logic to shift content of data storage registers. The key expansion circuit includes logic to determine a round key based upon an input symmetric key and data input, a previous round key, and a value from the constant generator. The constant generator includes logic to output a successive one of a list of constants each clock cycle, and to store the outputted constants in storage units. The number of storage units is less than the size of the list of constants.
摘要翻译：处理器包括输入电路和西门子分组密码。 Simon分组密码包括数据变换电路，恒定发生器和密钥扩展电路。数据变换电路包括移位数据存储寄存器的内容的逻辑。密钥扩展电路包括基于输入对称密钥和数据输入，先前的循环密钥和来自常量发生器的值来确定循环密钥的逻辑。常数发生器包括用于输出每个时钟周期的常数列表中的连续的一个的逻辑，并将输出的常数存储在存储单元中。存储单元的数量小于常量列表的大小。

23. 发明申请

US20140229741A1 Dual Composite Field Advanced Encryption Standard Memory Encryption Engine 审中-公开
标题翻译：双复合现场高级加密标准内存加密引擎
公开(公告)号：US20140229741A1
公开(公告)日：2014-08-14
申请号：US13993545
申请日：2011-12-30
申请人： Sanu K. Mathew , Shay Gueron , Ram K. Krishnamurthy
发明人： Sanu K. Mathew , Shay Gueron , Ram K. Krishnamurthy
IPC分类号： G06F21/72 , G06F21/60
CPC分类号： G06F21/72 , G06F21/60 , H04L9/0631 , H04L2209/122
摘要： A different set of polynomials may be selected for encryption and decryption accelerators. That is, different sets of polynomials are used for encryption and decryption, each set being chosen to use less area and deliver more power for a memory encryption engine. This is advantageous in some embodiments since memory read operations are typically more critical and latency sensitive than memory writes.
摘要翻译：可以为加密和解密加速器选择不同的多项式集合。也就是说，不同的多项式组用于加密和解密，每组被选择为使用较少的区域并为存储器加密引擎提供更多的功率。这在一些实施例中是有利的，因为存储器读取操作通常比存储器写入更为关键和延迟敏感。

24. 发明申请

US20140091832A1 INTEGRATED CIRCUITS HAVING ACCESSIBLE AND INACCESSIBLE PHYSICALLY UNCLONABLE FUNCTIONS 有权
标题翻译：具有可接受和不可接受的物理不可靠功能的集成电路
公开(公告)号：US20140091832A1
公开(公告)日：2014-04-03
申请号：US13631634
申请日：2012-09-28
申请人： Kevin C. Gotze , Gregory M. Iovino , Jiangtao Li , David Johnston , Sanu K. Mathew , George W. Cox , Anand Rajan
发明人： Kevin C. Gotze , Gregory M. Iovino , Jiangtao Li , David Johnston , Sanu K. Mathew , George W. Cox , Anand Rajan
IPC分类号： H03K19/003
CPC分类号： H03K19/003 , G09C1/00 , H04L9/0866 , H04L2209/12
摘要： An integrated circuit substrate of an aspect includes a plurality of exposed electrical contacts. The integrated circuit substrate also includes an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts. The integrated circuit substrate also includes an accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts. Other apparatus, methods, and systems are also disclosed.
摘要翻译：一方面的集成电路基板包括多个暴露的电触点。集成电路基板还包括不可接近的物理不可克隆功能（PUF）单元组，以生成不能通过暴露的电触点访问的不可访问的PUF位集合。集成电路基板还包括可访问的PUF单元组，以产生可通过暴露的电触点访问的可访问的PUF位组。还公开了其他装置，方法和系统。

25. 发明申请

US20100082718A1 COMBINED SET BIT COUNT AND DETECTOR LOGIC 有权
标题翻译：组合设置位计数和检测器逻辑
公开(公告)号：US20100082718A1
公开(公告)日：2010-04-01
申请号：US12242727
申请日：2008-09-30
申请人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
发明人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
IPC分类号： G06F7/00
CPC分类号： G06F7/74 , G06F7/607
摘要： A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).
摘要翻译：描述了PopCount和BitScan的合并数据路径。硬件电路包括用于PopCount功能的压缩器树，其由BitScan功能（例如，位扫描前向（BSF）或位扫描反向（BSR））重用。选择器逻辑使压缩器树能够基于微处理器指令对PopCount或BitScan操作的输入字进行操作。如果选择了BitScan操作，则输入字被编码。压缩器树接收输入字，对位进行操作，好像所有位具有相同的重要程度（例如，对于N位输入字，输入字被视为N个一位输入）。压缩器树电路的结果是表示与执行的操作有关的数字的二进制值（PopCount的设置位数，或通过扫描输入字所遇到的第一组位的位位置）。

26. 发明授权

US07592835B2 Co-processor having configurable logic blocks 有权
标题翻译：协处理器具有可配置的逻辑块
公开(公告)号：US07592835B2
公开(公告)日：2009-09-22
申请号：US11966307
申请日：2007-12-28
申请人： Amit Agarwal , Sanu K. Mathew , Ram K. Krishnamurthy , Rajaraman Ramanarayanan
发明人： Amit Agarwal , Sanu K. Mathew , Ram K. Krishnamurthy , Rajaraman Ramanarayanan
IPC分类号： H01L25/00
CPC分类号： H03K19/177
摘要： A co-processor system is provided that includes an array of configurable logic blocks (CLBs). Each CLB including a plurality of look-up tables and a plurality of adders. Each CLB may be dynamically reconfigurable to perform a plurality of logical functions.
摘要翻译：提供了包括可配置逻辑块（CLB）阵列的协处理器系统。每个CLB包括多个查找表和多个加法器。每个CLB可以是动态可重构的以执行多个逻辑功能。

27. 发明授权

US07509368B2 Sparse tree adder circuit 有权
标题翻译：稀疏树加法器电路
公开(公告)号：US07509368B2
公开(公告)日：2009-03-24
申请号：US11123702
申请日：2005-05-09
申请人： Mark A. Anders , Sanu K. Mathew , Nanda Siddaiah , Sapumal Wijeratne
发明人： Mark A. Anders , Sanu K. Mathew , Nanda Siddaiah , Sapumal Wijeratne
IPC分类号： G06F7/50
CPC分类号： G06F7/507 , G06F7/508
摘要： An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.
摘要翻译：提供了一种加法器电路，其包括传播和产生电路级以提供传播和产生信号;多个进位合并级，用于基于传播和产生信号提供进位信号;以及条件和发生器，以基于传播和产生信号。条件和生成器包括纹波进位门和异或逻辑门。加法器电路还包括多个多路复用器，用于接收进位信号和条件和，并且基于输入信号提供输出。

28. 发明授权

US07325024B2 Adder circuit with sense-amplifier multiplexer front-end 有权
标题翻译：加法器电路带有读出放大器多路复用器前端
公开(公告)号：US07325024B2
公开(公告)日：2008-01-29
申请号：US10728127
申请日：2003-12-04
申请人： Sanu K. Mathew , Mark A. Anders , Ram K. Krishnamurthy , Sapumal Wijeratne
发明人： Sanu K. Mathew , Mark A. Anders , Ram K. Krishnamurthy , Sapumal Wijeratne
IPC分类号： G06F7/50
CPC分类号： G06F7/507 , G06F7/506
摘要： An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.
摘要翻译：一个加法器电路包括多个选择器和一个加法器。选择器为加法器提供多个输入数据位。每个选择器包括复用网络和读出放大器的组合，以从多个输入值中选择以产生多个输入数据位。复用网络和读出放大器的组合在加法器的输入端作为状态保持元件，避免显式锁存级的开销。

29. 发明授权

US07188134B2 High-performance adder 有权
标题翻译：高性能加法器
公开(公告)号：US07188134B2
公开(公告)日：2007-03-06
申请号：US09967240
申请日：2001-09-28
申请人： Sanu K. Mathew , Ram K. Krishnamurthy
发明人： Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： G06F7/50
CPC分类号： G06F7/506 , G06F7/507
摘要： An adder for use in summing two binary numbers in an arithmetic logic unit of a processor. The adder includes a sparse carry-merge circuit adapted to generate a first predetermined number of carries and a plurality of intermediate carry generators coupled to the sparse carry merge circuit and adapted to generate a second predetermined number of carry signals. The adder further includes a plurality of conditional sum generators coupled to the intermediate carry generators and to the sparse carry-merge circuit to provide the sum of the two binary numbers. The adder may also include a multiplexer recovery circuit that enables a single rail dynamic implementation of the adder core.
摘要翻译：一种加法器，用于对处理器的算术逻辑单元中的两个二进制数进行求和。加法器包括适于生成第一预定数量的进位的稀疏进位合并电路和耦合到稀疏进位合并电路并适于产生第二预定数量进位信号的多个中间进位发生器。加法器还包括耦合到中间进位发生器和稀疏进位合并电路的多个条件和发生器，以提供两个二进制数的和。加法器还可以包括多路复用器恢复电路，其实现加法器核的单轨动态实现。

30. 发明授权

US07131055B2 Fast bit-parallel Viterbi decoder add-compare-select circuit 失效
标题翻译：快速位并行维特比解码器加比较选择电路
公开(公告)号：US07131055B2
公开(公告)日：2006-10-31
申请号：US10372121
申请日：2003-02-25
申请人： Sanu K. Mathew , Ram Krishnamurthy , Hoang Q. Dao
发明人： Sanu K. Mathew , Ram Krishnamurthy , Hoang Q. Dao
IPC分类号： H03M13/03
CPC分类号： H03M13/6502 , H03M13/4107
摘要： A Viterbi decoder includes an ACS unit that performs state metric updates for every symbol cycle. State metric updates involve adding the state metrics corresponding to a likely input symbol to the respective branch matrix, comparing the results of the additions to determine which is smaller, and selecting the smaller result for the next state metric. The ACS unit includes two parallel adders followed by a parallel comparator that generates a multiplexer-select signal. The outputs of the parallel adders are input into a multiplexer and the multiplexer-select signal is input into the multiplexer for a decision.
摘要翻译：维特比解码器包括对每个符号周期执行状态度量更新的ACS单元。状态度量更新涉及将对应于可能的输入符号的状态量度相加到相应的分支矩阵，比较添加的结果以确定哪个更小，并为下一状态度量选择较小的结果。 ACS单元包括两个并行加法器，其后是并行比较器，其产生多路选择器选择信号。并行加法器的输出被输入到多路复用器中，并且多路复用器选择信号被输入到多路复用器中用于决定。

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