专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20130318364A1 PROCESSOR NOISE MITIGATION USING DIFFERENTIAL CRITICAL PATH MONITORING 有权
标题翻译：使用差分关键路径监测的处理器噪声减轻
公开(公告)号：US20130318364A1
公开(公告)日：2013-11-28
申请号：US13479797
申请日：2012-05-24
申请人： Robert W. Berry, JR. , Michael S. Floyd , Jarom Pena , Ryan J. Pennington , Catherine Sherry
发明人： Robert W. Berry, JR. , Michael S. Floyd , Jarom Pena , Ryan J. Pennington , Catherine Sherry
IPC分类号： G06F1/26
CPC分类号： G06F1/28 , G06F1/26 , G06F11/3062
摘要： An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.
摘要翻译：提供了一种处理器电源噪声抑制方法。在一个方面，该方法包括可操作地耦合到处理器以执行程序操作的中央计算单元。该方法还包括校准电路，其适于确定要用于通过使用检测电路动态执行的比较的处理器上的第一阈值。一种检测电路，适用于动态地监视处理器的系统操作并指示是否违反了第一阈值，还提供了一种适于在一个或多个电压感测测量违反第一阈值时防止电压下降的计数电路。

22. 发明申请

US20080059103A1 System and Method for Implementing a Programmable DMA Master With Date Checking Utilizing a Drone System Controller 失效
标题翻译：使用无人机系统控制器实现可编程DMA主机的日期检查的系统和方法
公开(公告)号：US20080059103A1
公开(公告)日：2008-03-06
申请号：US11470282
申请日：2006-09-06
申请人： Robert W. Berry , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
发明人： Robert W. Berry , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
IPC分类号： G06F19/00 , G11C29/00
CPC分类号： G11C29/48 , G06F11/26
摘要： A method, system, and computer-usable medium for implementing a programmable DMA master with date checking utilizing a drone system controller. According to a preferred embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.
摘要翻译：一种方法，系统和计算机可用介质，用于使用无人机系统控制器实现具有日期检查的可编程DMA主机。根据本发明的优选实施例，无人机处理器生成随机数据的集合，并将随机数据集合的第一和第二副本存储在无人机存储器中的第一和第二存储器位置中。无人机处理器将随机数据集合的第三副本写入处理器存储器。当无人机处理器从处理器存储器检索第三副本时，无人机处理器将第三副本写入无人机存储器中的第二存储器位置。当无人机处理器将第一副本与第三副本进行比较时，将比较结果写入无人机处理器内的状态位置。

23. 发明授权

US4189265A Positive chip control insert 失效
标题翻译：正芯片控制插入
公开(公告)号：US4189265A
公开(公告)日：1980-02-19
申请号：US942549
申请日：1978-09-15
申请人： Leonard R. Arnold , Robert W. Berry, Jr.
发明人： Leonard R. Arnold , Robert W. Berry, Jr.
IPC分类号： B23B27/14 , B26D1/12
CPC分类号： B23B27/143 , B23B2200/085 , B23B2200/204 , B23B2200/321 , Y10T407/235
摘要： An indexable, insert for single-point and multiple-point negative rake holding devices which convert the cutting point to a positive cutting geometry. The insert has straight descending and widening V-shaped grooves from each corner along the adjacent sides, each groove modulating into a low angle straight section which rises abruptly into a radial cross-ridge at the midpoint of the groove, the cross-ridge rising to a crest line below the plane of the resulting island created by the grooves around the insert.
摘要翻译：用于将切割点转换为正切削几何的单点和多点负耙保持装置的可转位插入件。插入件沿着相邻的侧面从每个拐角处具有直下降和变宽的V形凹槽，每个凹槽调制成一个低角度的直线段，其在槽的中点突然地上升到径向的交叉脊中，在由所述插入件周围的槽形成的所产生的岛的平面下方的波峰线。

24. 发明授权

US4083416A Collapsible cutterhead for drilling upward 失效
标题翻译：可折叠的刀头向上钻
公开(公告)号：US4083416A
公开(公告)日：1978-04-11
申请号：US787283
申请日：1977-04-13
申请人： Norman H. Still , Robert W. Berry, Jr.
发明人： Norman H. Still , Robert W. Berry, Jr.
IPC分类号： E21B7/20 , E21B10/34 , E21B10/66 , E21B9/00
CPC分类号： E21B10/34 , E21B10/66 , E21B7/20
摘要： A cutterhead adapted for drilling a hole upwardly in the earth, and to then be withdrawn downwardly through a casing which is inserted underneath the cutterhead, characterized by gauge cutters which are pivotally mounted on the cutterhead so that they will pivot upward and radially inward when the cutterhead is drawn into the casing, and also characterized by stabilizer rollers mounted on removable frames that can be detached.
摘要翻译：一种用于在地球上向上钻孔的刀头，然后通过插入刀架下方的壳体向下抽出，其特征在于，在刀盘上枢转地安装有量规切割器，使得当刀头向上和向内转动时刀头被拉入外壳，其特征还在于安装在可拆卸的可拆卸框架上的稳定辊。

25. 发明授权

US09020779B2 Detecting cross-talk on processor links 有权
标题翻译：检测处理器链路上的串扰
公开(公告)号：US09020779B2
公开(公告)日：2015-04-28
申请号：US13281097
申请日：2011-10-25
申请人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
发明人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F11/263 , G06F9/30 , G06F11/34
CPC分类号： G06F9/30145 , G06F9/30 , G06F11/3409 , G06F11/3414 , G06F11/3466 , G06F11/349
摘要： A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.
摘要翻译：多个处理器链路中的第一个处理器链路的多个数据通路中的第一个被确定为对于多个数据通道具有最弱的基本性能测量。经由剩余处理器链路的第一组发送切换数据模式，并且经由剩余处理器链路的第二组发送安静数据模式。如果第一数据线的性能相对于相应的基本性能测量增加，则剩余处理器链路的第一组从剩余处理器链路中消除。如果第一数据通道的性能相对于相应的基本性能测量值降低，则剩余处理器链路的第二组从剩余处理器链路中消除。重复执行上述操作，直到识别出被确定为降低多个数据通道中的第一个数据通道的性能的攻击者处理器链路。

26. 发明授权

US08826092B2 Characterization and validation of processor links 有权
公开(公告)号：US08826092B2
公开(公告)日：2014-09-02
申请号：US13281081
申请日：2011-10-25
申请人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
发明人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F11/00 , G01R31/319 , G06F11/22
CPC分类号： G06F11/3089 , G01R31/31926 , G06F9/30 , G06F9/30007 , G06F11/22 , G06F11/221 , G06F11/3409 , G06F11/3414 , G06F11/349 , G06F15/00
摘要： A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

27. 发明申请

US20120330616A1 FREQUENCY GUARD BAND VALIDATION OF PROCESSORS 有权
标题翻译：加工商的频率防护带验证
公开(公告)号：US20120330616A1
公开(公告)日：2012-12-27
申请号：US13170150
申请日：2011-06-27
申请人： Robert W. Berry , Diyanesh B. Chinnakkonda , Prasanna Jayaraman , Tony E. Sawan
发明人： Robert W. Berry , Diyanesh B. Chinnakkonda , Prasanna Jayaraman , Tony E. Sawan
IPC分类号： G06F11/30
CPC分类号： G01R31/2879 , G06F11/24
摘要： A frequency guard band validation unit can determine whether at least one of a plurality of previously validated processors was validated on a first system having a substantially similar configuration as a second system in which an unvalidated processor is being tested. If at least one of the plurality of previously validated processors was validated on the first system, a validation start frequency associated with the unvalidated processor can be computed based, at least in part, on system parametric data associated with a subset of the plurality of previously validated processors that were validated on the first system. Otherwise, the validation start frequency associated with the unvalidated processor is computed based, at least in part, on tester parametric data associated with the unvalidated processor. Validation of the guard band frequency for the unvalidated processor is initiated at the validation start frequency. This can reduce the overall validation cycle time.
摘要翻译：频率保护频带验证单元可以确定在具有基本相似配置的第一系统上验证多个先前验证的处理器中的至少一个是否是正在测试未验证的处理器的第二系统。如果多个先前验证的处理器中的至少一个在第一系统上被验证，则可以至少部分地基于与先前多个先前验证的处理器的子集相关联的系统参数数据来计算与未验证的处理器相关联的验证开始频率在第一个系统上验证的经过验证的处理器。否则，至少部分地基于与未经验证的处理器相关联的测试仪参数数据来计算与未验证的处理器相关联的验证开始频率。无效处理器的保护频带频率的验证在验证开始频率处启动。这可以减少总体验证周期时间。

28. 发明授权

US08165847B2 Implementing a programmable DMA master with write inconsistency determination 失效
标题翻译：实现具有写入不一致性确定的可编程DMA主机
公开(公告)号：US08165847B2
公开(公告)日：2012-04-24
申请号：US12187199
申请日：2008-08-06
申请人： Robert W. Berry, Jr. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
发明人： Robert W. Berry, Jr. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
IPC分类号： G06F11/30 , G11C29/00
CPC分类号： G11C29/48 , G06F11/26
摘要： A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.
摘要翻译：一种用于使用无人机系统控制器实现具有数据检查的可编程DMA主机的方法，系统和计算机可用介质。根据本发明的实施例，无人机处理器生成随机数据的集合，并将随机数据的集合的第一和第二副本存储在无人机存储器中的第一和第二存储器位置中。无人机处理器将随机数据集合的第三副本写入处理器存储器。当无人机处理器从处理器存储器检索第三副本时，无人机处理器将第三副本写入无人机存储器中的第二存储器位置。当无人机处理器将第一副本与第三副本进行比较时，将比较结果写入无人机处理器内的状态位置。

29. 发明申请

US20100250943A1 METHOD FOR SECURITY IN ELECTRONICALLY FUSED ENCRYPTION KEYS 有权
标题翻译：电子加热加压棒的安全方法
公开(公告)号：US20100250943A1
公开(公告)日：2010-09-30
申请号：US12413016
申请日：2009-03-27
申请人： Robert W. Berry, JR. , Jonathan J. DeMent , John S. Liberty
发明人： Robert W. Berry, JR. , Jonathan J. DeMent , John S. Liberty
IPC分类号： H04L9/32 , G06F11/00 , H04L9/06
CPC分类号： H04L9/32 , G06F21/75 , H04L2209/34 , H04L2209/56
摘要： A method for electronically fused encryption key security includes inserting a plurality of inverters between a bank of security fuses and a fuse sense logic module. The method also includes sensing an activated set of the bank of security fuses and the plurality of inverters. The method further includes comparing the sensed activated set of the bank of security fuses and the plurality of inverters with a software key to determine whether at least a substantial match is made.
摘要翻译：一种用于电子融合加密密钥安全性的方法包括在安全保险丝组和熔丝检测逻辑模块之间插入多个逆变器。该方法还包括感测安全熔断器组和多个逆变器的激活组。该方法还包括将感测到的安全熔断器组和多个逆变器的激活组与软件密钥进行比较，以确定是否至少进行了实质的匹配。

30. 发明申请

US20100161921A1 FLASH ROM PROGRAMMING 有权
标题翻译：闪存编程
公开(公告)号：US20100161921A1
公开(公告)日：2010-06-24
申请号：US12339018
申请日：2008-12-18
申请人： Robert W. Berry, JR. , Michael Criscolo , Michael T. Saunders
发明人： Robert W. Berry, JR. , Michael Criscolo , Michael T. Saunders
IPC分类号： G06F13/00
CPC分类号： G11C16/102 , G06F8/66
摘要： A method comprises providing a golden ROM unit comprising known good ROM code. The golden ROM is coupled to a ROM socket of a target system. The target system is booted, wherein booting comprises providing power to the target system and independently providing power to the ROM socket. The known good ROM code is loaded from the golden ROM to a system memory of the target system. Power is removed from the ROM socket and the golden ROM is decoupled from the ROM socket. A first subject ROM is coupled to the ROM socket. Power is provided to the ROM socket and the first subject ROM is programmed with the known good ROM code.
摘要翻译：一种方法包括提供包括已知的良好ROM码的金色ROM单元。金色ROM耦合到目标系统的ROM插槽。引导目标系统，其中引导包括向目标系统提供电力并且独立地向ROM插槽供电。已知的良好ROM代码从金色ROM加载到目标系统的系统内存。电源从ROM插槽中取出，金色ROM从ROM插槽中脱离。第一主题ROM耦合到ROM插槽。电源提供给ROM插槽，第一个对象ROM用已知的良好的ROM代码进行编程。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式