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21. 发明申请

US20060159200A1 FRONT END INTERFACE FOR DATA RECEIVER 失效
标题翻译：数据接收器的前端接口
公开(公告)号：US20060159200A1
公开(公告)日：2006-07-20
申请号：US10905705
申请日：2005-01-18
申请人： Louis Hsu , Matt Cordrey-Gale , James Mason , Phillip Murfet , Karl Selander , Michael Sorna , Huihao Xu
发明人： Louis Hsu , Matt Cordrey-Gale , James Mason , Phillip Murfet , Karl Selander , Michael Sorna , Huihao Xu
IPC分类号： H04L27/22
CPC分类号： H04L25/0274 , H04L25/0296
摘要： A data receiver is provided which includes a front end interface circuit having an alternating current (AC) transmission receiving mode and a direct current (DC) transmission receiving mode. The front end interface circuit includes an offset compensation circuit operable to compensate a DC voltage offset between a pair of differential signals input to the data receiver. The front end interface circuit further includes an AC/DC selection unit operable to switch between (a) the DC transmission receiving mode, and (b) the AC transmission receiving mode, such that the data receiver is operable in (i) the DC transmission mode in which the offset compensation circuit is disabled, (ii) the DC transmission mode in which the offset compensation circuit is enabled, (iii) the AC transmission mode in which the offset compensation circuit is disabled, and (iv) the AC transmission receiving mode in which the offset compensation circuit is enabled.
摘要翻译：提供一种数据接收器，其包括具有交流（AC）发送接收模式和直流（DC）发送接收模式的前端接口电路。前端接口电路包括偏移补偿电路，其可操作以补偿输入到数据接收器的一对差分信号之间的直流电压偏移。前端接口电路还包括可操作以在（a）直流发送接收模式和（b）交流发送接收模式之间切换的AC / DC选择单元，使得数据接收器可操作于（i）直流传输偏移补偿电路被禁用的模式，（ii）使能偏移补偿电路的直流传输模式，（iii）偏移补偿电路被禁用的AC传输模式，以及（iv）AC传输接收偏移补偿电路使能的模式。

22. 发明申请

US20060158229A1 IMPROVED SIGNAL DETECTOR FOR HIGH-SPEED SERDES 失效
标题翻译：改进的高速伺服信号检测器
公开(公告)号：US20060158229A1
公开(公告)日：2006-07-20
申请号：US10905704
申请日：2005-01-18
申请人： Louis Hsu , Karl Selander , Michael Sorna
发明人： Louis Hsu , Karl Selander , Michael Sorna
IPC分类号： H03K5/19
CPC分类号： H03K5/19 , G01R19/165
摘要： An improved signal detector system implementable in a high-speed SerDes receiver core that is able to detect valid signals from noise signals with a much tighter tolerance. The signal detector system improves upon the prior art designs by implementing modifications including: (1) the use of two peaking amplifiers for both (differential) input signals and reference to track and cancel gain variation; and, (2) the reduction of current mirroring stages to cut down current mapping error.
摘要翻译：改进的信号检测器系统可实现在高速SerDes接收机核心中，能够以更严格的公差检测来自噪声信号的有效信号。信号检测器系统通过实施修改来改进现有技术的设计，包括：（1）使用两个峰值放大器用于（差分）输入信号和参考跟踪和消除增益变化; 和（2）减少当前镜像阶段以减少当前的映射误差。

23. 发明申请

US20060110851A1 Methods for forming co-planar wafer-scale chip packages 有权
标题翻译：用于形成共面晶片级芯片封装的方法
公开(公告)号：US20060110851A1
公开(公告)日：2006-05-25
申请号：US10994494
申请日：2004-11-20
申请人： Lloyd Burrell , Howard Chen , Louis Hsu , Wolfgang Sauter
发明人： Lloyd Burrell , Howard Chen , Louis Hsu , Wolfgang Sauter
IPC分类号： H01L21/48 , H01L21/50
CPC分类号： H01L23/5389 , H01L21/52 , H01L23/147 , H01L23/5385 , H01L2221/68322 , H01L2221/68345 , H01L2924/0002 , H01L2924/1433 , H01L2924/00
摘要： Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.
摘要翻译：提出了用于形成共面多芯片晶片级封装的经济方法。部分晶片接合和部分晶片切割技术用于制造芯片以及口袋。然后将完成的芯片安装在载体基板的相应凹穴中，并且芯片之间的全局互连形成在成品芯片的顶部平坦表面上。所提出的方法促进了用不同工艺步骤和材料制造的芯片的集成。不需要使用诸如化学机械抛光剂的平面化处理来平坦化芯片的顶表面。由于芯片精确地对准并且所有芯片都朝上安装，所以模块准备好进行全局布线，从而不需要将芯片从倒置的位置翻转。

24. 发明申请

US20060109117A1 Apparatus and Method of Intelligent Multistage System Deactivation 审中-公开
标题翻译：智能多级系统停用的装置与方法
公开(公告)号：US20060109117A1
公开(公告)日：2006-05-25
申请号：US10904664
申请日：2004-11-22
申请人： Louis Hsu , Lawrence Clevenger , Carl Radens , Kwong Wong , Chih-Chao Yang , Timothy Dalton
发明人： Louis Hsu , Lawrence Clevenger , Carl Radens , Kwong Wong , Chih-Chao Yang , Timothy Dalton
IPC分类号： G08B13/14
CPC分类号： G06F21/554 , G06F21/81 , G06F21/86
摘要： A deactivation management unit for facilitating an intelligent multistage system deactivation process where the deactivation management unit is flexible, facilitates recovery, and renders reverse engineering nearly impossible after the system has been permanently deactivated.
摘要翻译：一种停用管理单元，用于促进智能多级系统停用过程，其中停用管理单元是灵活的，便于恢复，并且在系统被永久停用之后几乎不可能实现逆向工程。

25. 发明申请

US20060102223A1 Integrated thermoelectric cooling devices and methods for fabricating same 有权
公开(公告)号：US20060102223A1
公开(公告)日：2006-05-18
申请号：US10988015
申请日：2004-11-12
申请人： Howard Chen , Richard Chu , Louis Hsu
发明人： Howard Chen , Richard Chu , Louis Hsu
IPC分类号： H01L35/34 , H01L35/30 , H01L37/00
CPC分类号： H01L35/34 , H01L23/38 , H01L27/16 , H01L35/32 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： Semiconductor integrated thermoelectric devices are provided, which are formed having high-density arrays of thermoelectric (TE) elements using semiconductor thin-film and VLSI (very large scale integration) fabrication processes. Thermoelectric devices can be either separately formed and bonded to semiconductor chips, or integrally formed within the non-active surface of semiconductor chips, for example.

26. 发明申请

US20060006166A1 On-chip power supply regulator and temperature control system 失效
标题翻译：片上电源调节器和温度控制系统
公开(公告)号：US20060006166A1
公开(公告)日：2006-01-12
申请号：US10884933
申请日：2004-07-06
申请人： Howard Chen , William Ferrante , Louis Hsu , Carl Radens
发明人： Howard Chen , William Ferrante , Louis Hsu , Carl Radens
IPC分类号： H05B1/02 , H05B3/00
CPC分类号： G05D23/20 , G05D23/1931 , Y10T307/469
摘要： An on-chip temperature control system includes a temperature sensor, which monitors a temperature of a chip, and a hysteresis comparator which checks whether the temperature is in an acceptable range. A reference adjustment circuit is responsive to the hysteresis comparator to adjust an on-chip voltage to control the temperature locally by adjusting a local supply voltage, if the temperature is out of range.
摘要翻译：片上温度控制系统包括监测芯片温度的温度传感器和检查温度是否在可接受范围内的滞后比较器。如果温度超出范围，参考调节电路响应于迟滞比较器来调节片上电压以局部地调节局部电源电压来控制温度。

27. 发明申请

US20050260801A1 High performance FET with elevated source/drain region 失效
标题翻译：具有升高的源极/漏极区域的高性能FET
公开(公告)号：US20050260801A1
公开(公告)日：2005-11-24
申请号：US10996866
申请日：2004-11-24
申请人： Rama Divakaruni , Louis Hsu , Rajiv Joshi , Carl Radens
发明人： Rama Divakaruni , Louis Hsu , Rajiv Joshi , Carl Radens
IPC分类号： H01L21/336 , H01L29/45 , H01L29/76 , H01L29/786
CPC分类号： H01L29/66553 , H01L29/458 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66772 , H01L29/7842 , H01L29/78618 , H01L29/78684
摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.
摘要翻译：包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 FET包括在绝缘体层上的每个端部（例如，在绝缘体上的超薄绝缘体（SOI））芯片上的源极/漏极（RSD）区域上升的薄沟道。在FET的每个端部，即在RSD区域的末端处的隔离沟槽隔离并限定FET岛。每个RSD区域的绝缘侧壁将RSD区域之间的FET栅极夹在中间。栅极电介质可以是高K电介质。 RSD区域上和可选地在栅极上的杀菌剂降低了器件电阻。

28. 发明申请

US20050199977A1 Structure and method for forming a dielectric chamber and electronic device including the dielectric chamber 有权
公开(公告)号：US20050199977A1
公开(公告)日：2005-09-15
申请号：US11129325
申请日：2005-05-16
申请人： George Feng , Louis Hsu , Rajiv Joshi
发明人： George Feng , Louis Hsu , Rajiv Joshi
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/522 , H01L29/00
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

29. 发明授权

US06912665B2 Automatic timing analyzer 失效
标题翻译：自动定时分析仪
公开(公告)号：US06912665B2
公开(公告)日：2005-06-28
申请号：US09827026
申请日：2001-04-05
申请人： Wayne F. Ellis , John A. Fifield , Louis Hsu , William V. Huott
发明人： Wayne F. Ellis , John A. Fifield , Louis Hsu , William V. Huott
IPC分类号： G01R31/317 , G06F1/04 , G06F11/00 , G11C29/02
CPC分类号： G11C29/028 , G01R31/31725 , G11C29/02 , G11C29/50012
摘要： A test methodology is used to conduct an automatic chip timing analysis in coarse and fine resolution steps. Timing adjustment circuits implement coarse timing adjustment and fine timing adjustment for chip timing analysis. Timings such as clock, address and control inputs to a memory system can be digitally adjusted with respect to each other. A timer circuit is provided with a counter so that an incremental or decremental timing analysis can be carried out with a specific timing step. An algorithm is implemented which provides an effective, low-cost and accurate timing analysis. A nested loop is set up in the BIST where all possibilities of timing relationships between two or more signals can be applied to a device under test, and weaknesses, or failing timing conditions, can be found.
摘要翻译：测试方法用于在粗细和精细分辨率步骤中进行自动芯片定时分析。定时调整电路实现了芯片定时分析的粗略时序调整和精细定时调整。诸如时钟，地址和对存储器系统的控制输入的时序可以相对于彼此数字地调整。定时器电路设有计数器，使得可以用特定的定时步骤执行增量或递减定时分析。实现了一种提供有效，低成本和准确的时序分析的算法。在BIST中建立了嵌套循环，其中可以将两个或更多个信号之间的时序关系的所有可能性应用于被测设备，并且可以找到弱点或失败的时序条件。

30. 发明申请

US20050112811A1 ULTRA-THIN SOI MOSFET METHOD AND STRUCTURE 失效
标题翻译：超薄SOI MOSFET方法和结构
公开(公告)号：US20050112811A1
公开(公告)日：2005-05-26
申请号：US10707200
申请日：2003-11-26
申请人： Louis Hsu , Carl Radens , Ramachandra Divakaruni
发明人： Louis Hsu , Carl Radens , Ramachandra Divakaruni
IPC分类号： H01L21/336 , H01L21/762 , H01L29/45 , H01L21/8234
CPC分类号： H01L29/66772 , H01L21/76283 , H01L29/458 , H01L29/66545
摘要： An ultra-thin, scaleable MOSFET transistor and fabrication method are described. The transistor features fully self-aligned, raised source/drain junctions on a thin SOI wafer and exhibits low contact resistance, low gate resistance and good device isolation characteristic. No extra lithographic mask steps are required beyond those required by conventional processes. The transistor is completely “bracketed” or surrounded by STI (shallow trench isolation), providing inherent isolation between it and any other devices on the SOI wafer. Gate sidewall spacers are formed outside of the gate area so that the scalability is limited solely by lithography resolution.
摘要翻译：描述了一种超薄的可扩展MOSFET晶体管和制造方法。晶体管在薄SOI晶圆上具有完全自对准的升高的源极/漏极结，并且具有低接触电阻，低栅极电阻和良好的器件隔离特性。不需要额外的光刻掩模步骤，超出传统工艺所需要的步骤。晶体管完全“包围”或被STI（浅沟槽隔离）包围，提供了SOI晶片上任何其他器件之间的固有隔离。栅极侧壁间隔物形成在栅极区域的外部，从而可扩展性仅由光刻分辨率限制。

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