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21. 发明申请

US20050146975A1 Method and apparatus for multiple row caches per bank 有权
标题翻译：每行多行缓存的方法和装置
公开(公告)号：US20050146975A1
公开(公告)日：2005-07-07
申请号：US10750038
申请日：2003-12-30
申请人： John Halbert , Robert Ellis , Kuljit Bains , Chris Freeman
发明人： John Halbert , Robert Ellis , Kuljit Bains , Chris Freeman
IPC分类号： G11C7/10 , G11C11/4096 , G11C8/00
CPC分类号： G11C7/1012 , G11C7/1048 , G11C7/1051 , G11C11/4096 , G11C2207/005
摘要： Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to read the contents of that at least one row through a read operation causing the data to read from the row of sense amplifiers versus from the row of memory cells, directly.
摘要翻译：提供和使用隔离器组，以使得能够通过与子阵列相关联的一行读出放大器将存储器件组的子阵列内的至少一行存储器单元的内容缓存以使得能够更快地访问内容通过读取操作使至少一行直接从存储器单元行读取数据从读出放大器行读取。

22. 发明申请

US20050081085A1 Memory buffer device integrating ECC 有权
标题翻译：集成ECC的内存缓冲设备
公开(公告)号：US20050081085A1
公开(公告)日：2005-04-14
申请号：US10674320
申请日：2003-09-29
申请人： Robert Ellis , Kuljit Bains , Chris Freeman , John Halbert
发明人： Robert Ellis , Kuljit Bains , Chris Freeman , John Halbert
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1044
摘要： Apparatus and method to carry out checks for memory errors within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.
摘要翻译：在存储器总线上没有活动的情况下，与存储器控制器独立地对存储器件内的存储器错误执行检查的装置和方法，该存储器总线将存储器装置耦合到涉及存储器件的存储器控制器。

23. 发明申请

US20130346684A1 METHOD, APPARATUS AND SYSTEM FOR A PER-DRAM ADDRESSABILITY MODE 审中-公开
标题翻译：方法，设备和系统，用于存储器可寻址模式
公开(公告)号：US20130346684A1
公开(公告)日：2013-12-26
申请号：US13531368
申请日：2012-06-22
申请人： Kuljit Bains
发明人： Kuljit Bains
IPC分类号： G06F12/00
CPC分类号： G11C7/1045 , G11C7/109 , G11C11/4096
摘要： Techniques and mechanisms for programming an operation mode of a dynamic random access memory (DRAM) device. In an embodiment, a memory controller stores a value in a mode register of a DRAM device, the value specifying whether a per-DRAM addressability (PDA) mode of the DRAM device is enabled. An external contact of the DRAM device is coupled to the memory controller device via a signal line of a data bus. In another embodiment, the memory controller sends a signal to the external contact while the PDA mode of the DRAM device is enabled, the signal to specify whether one or more features of the DRAM device are programmable.
摘要翻译：用于编程动态随机存取存储器（DRAM）设备的操作模式的技术和机制。在一个实施例中，存储器控制器将值存储在DRAM器件的模式寄存器中，该值指定DRAM器件的每DRAM可寻址（PDA）模式是否被使能。 DRAM器件的外部触点经由数据总线的信号线耦合到存储器控制器装置。在另一个实施例中，存储器控制器在DRAM器件的PDA模式被使能的同时向外部触点发送信号，该信号指定DRAM器件的一个或多个特征是否可编程。

24. 发明授权

US07404055B2 Memory transfer with early access to critical portion 有权
标题翻译：具有早期访问关键部分的内存传输
公开(公告)号：US07404055B2
公开(公告)日：2008-07-22
申请号：US11392471
申请日：2006-03-28
申请人： Kuljit Bains , John Halbert , Greg Lemos , Randy Osborne
发明人： Kuljit Bains , John Halbert , Greg Lemos , Randy Osborne
IPC分类号： G06F12/00
CPC分类号： G06F13/1678
摘要： In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred from the second memory agent back to the first memory agent in a second format having a second width, where the critical portion is included in a first frame. The critical portion may include a cacheline mapped over a memory device rank. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，数据可以以具有第一宽度的第一格式从第一存储器传送到第二存储器代理，并且数据的至少关键部分可以从第二存储器代理返回到第一存储器具有第二宽度的第二格式，其中临界部分包括在第一帧中。关键部分可以包括在存储器设备等级上映射的高速缓存线。描述和要求保护其他实施例。

25. 发明申请

US20070130374A1 Multiported memory with configurable ports 审中-公开
标题翻译：具有可配置端口的多端口存储器
公开(公告)号：US20070130374A1
公开(公告)日：2007-06-07
申请号：US11280837
申请日：2005-11-15
申请人： Kuljit Bains , John Halbert , Randy Osborne
发明人： Kuljit Bains , John Halbert , Randy Osborne
IPC分类号： G06F3/00
CPC分类号： G06F13/1694
摘要： In some embodiments, a chip includes memory banks and data ports, including at least first and second data ports, coupled to the memory banks. The chip also includes control circuitry to control a configuration of the first data port to be in one of multiple configurations in response to a configuration command, wherein the available configurations for the first data port include at least two of the following: whether the first data port (1) may only be used for read transactions, (2) may only be used for write transactions, or (3) may be used for either read or write transactions while in the configuration. Other embodiments are described.
摘要翻译：在一些实施例中，芯片包括耦合到存储体的存储器组和数据端口，包括至少第一和第二数据端口。该芯片还包括控制电路，用于响应于配置命令将第一数据端口的配置控制为多个配置之一，其中第一数据端口的可用配置包括以下中的至少两个：第一数据端口（1）只能用于读取事务，（2）只能用于写入事务，或者（3）可以在配置中用于读取或写入事务。描述其他实施例。

26. 发明申请

US20060239095A1 Memory device communication using system memory bus 有权
标题翻译：使用系统内存总线的内存设备通讯
公开(公告)号：US20060239095A1
公开(公告)日：2006-10-26
申请号：US11093705
申请日：2005-03-30
申请人： Jun Shi , Sandeep Jain , Animesh Mishra , Kuljit Bains , David Wyatt , Thomas Skelton , Bill Nale
发明人： Jun Shi , Sandeep Jain , Animesh Mishra , Kuljit Bains , David Wyatt , Thomas Skelton , Bill Nale
IPC分类号： G11C7/00
CPC分类号： G11C7/04 , G11C7/1045 , G11C11/4076
摘要： Data regarding physical parameters and security and commands to send such data can be communicated between a memory device and a memory controller using a memory bus connected between the two. In one embodiment, the invention includes receiving a first command at a memory device on a memory bus, the first command being other than a read or write command, and receiving a second command together with the first command, the second command to be initiated using lines that are not used by the first command.
摘要翻译：关于物理参数和安全性的数据以及发送这样的数据的命令可以使用连接在两者之间的存储器总线在存储器件和存储器控制器之间传送。在一个实施例中，本发明包括在存储器总线上的存储器件处接收第一命令，第一命令不同于读取或写入命令，并且与第一命令一起接收第二命令，使用第一个命令未使用的行。

27. 发明申请

US20050259480A1 Method and apparatus for providing debug functionality in a buffered memory channel 有权
标题翻译：用于在缓冲存储器通道中提供调试功能的方法和装置
公开(公告)号：US20050259480A1
公开(公告)日：2005-11-24
申请号：US11192249
申请日：2005-07-27
申请人： Kuljit Bains , Robert Ellis , Chris Freeman , John Halbert , David Zimmerman
发明人： Kuljit Bains , Robert Ellis , Chris Freeman , John Halbert , David Zimmerman
IPC分类号： G11C5/00 , G11C29/48 , G11C29/56
CPC分类号： G11C29/48 , G11C29/56 , G11C2029/5602
摘要： Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.
摘要翻译：本发明的一些实施例使得驻留在存储器模块上的存储器设备的调试功能能够通过缓冲器芯片从存储器总线缓冲。一些实施例将来自耦合到缓冲器芯片和存储器总线之间的高速接口的测试仪的连接器信号映射到缓冲器芯片和存储器件之间的接口。在测试模式期间，一些实施例绕过缓冲芯片的正常操作电路并提供与存储器件的直接连接。其他实施例使用缓冲芯片的现有架构将高速引脚转换成低速引脚并将其映射到连接到存储器件的引脚。在权利要求中描述了其它实施例。

28. 发明授权

US09355688B2 Adaptive voltage input to a charge pump 有权
标题翻译：自适应电压输入到电荷泵
公开(公告)号：US09355688B2
公开(公告)日：2016-05-31
申请号：US13976791
申请日：2012-05-08
申请人： Kuljit Bains , George Vergis
发明人： Kuljit Bains , George Vergis
IPC分类号： G05F1/10 , G11C5/14 , G11C11/4074 , G11C29/02
CPC分类号： G11C5/145 , G11C11/4074 , G11C29/021 , G11C29/028
摘要： A memory subsystem includes an adaptive output voltage to provide a voltage based on a power profile of a memory device of the memory subsystem. A charge pump increases the voltage to a level needed to write data to the memory device. The voltage provided is based on the power profile of the memory device, which indicates a voltage level that provides good efficiency for the charge pump, and is within maximum levels for the memory device. The voltage can be higher than a nominal voltage indicated for the memory device in a specification.
摘要翻译：存储器子系统包括自适应输出电压，以基于存储器子系统的存储器件的功率曲线来提供电压。电荷泵将电压提高到将数据写入存储器件所需的水平。所提供的电压基于存储器件的功率曲线，其指示为电荷泵提供良好效率的电压电平，并且在存储器件的最大电平内。电压可以高于规范中为存储器件指示的额定电压。

29. 发明授权

US09117544B2 Row hammer refresh command 有权
标题翻译：行锤刷新命令
公开(公告)号：US09117544B2
公开(公告)日：2015-08-25
申请号：US14068677
申请日：2013-10-31
申请人： Kuljit Bains , John Halbert , Christopher Mozak , Theodore Schoenborn , Zvika Greenfield
发明人： Kuljit Bains , John Halbert , Christopher Mozak , Theodore Schoenborn , Zvika Greenfield
IPC分类号： G06F13/10 , G11C11/406 , G11C7/02
CPC分类号： G11C11/40615 , G11C7/02 , G11C11/40611 , G11C11/40622
摘要： A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.
摘要翻译：内存控制器发出目标刷新命令。存储器件的特定行可以是重复访问的目标。当行在时间阈值（也称为“锤击”或“行锤事件”）中重复访问时，物理上相邻的行（“受害者”行）可能会遭遇数据损坏。存储器控制器接收行敲击事件的指示，识别与行锤事件相关联的行，并且将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

30. 发明申请

US20150109871A1 ROW HAMMER MONITORING BASED ON STORED ROW HAMMER THRESHOLD VALUE 有权
标题翻译：基于存储的RAM HAMMER阈值的ROW HAMMER监测
公开(公告)号：US20150109871A1
公开(公告)日：2015-04-23
申请号：US14108830
申请日：2013-12-17
申请人： Kuljit BAINS , John Halbert
发明人： Kuljit BAINS , John Halbert
IPC分类号： G11C11/4078 , G11C11/406
CPC分类号： G11C11/4078 , G06F13/1636 , G11C11/406 , G11C11/40611 , G11C11/408 , G11C29/50 , G11C29/50012 , G11C2029/0409
摘要： Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to it row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.
摘要翻译：存储器子系统的检测逻辑获得存储器设备的阈值，该存储器设备指示在时间窗口内的数量的访问，导致物理上相邻的行上的数据损坏风险。检测逻辑从存储器件的配置信息的寄存器获得阈值，并且可以是存储器件本身的寄存器和/或可以是存储器件所属的存储器模块的配置存储设备的条目。检测逻辑确定存储器件的行的访问次数是否超过阈值。响应于检测到的访问次数超过阈值，检测逻辑可以产生触发以使存储器件执行针对物理上相邻的受害者行的刷新。

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