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21. 发明申请

US20090179787A1 COMPARATOR AND A/D CONVERTER 有权
标题翻译：比较器和A / D转换器
公开(公告)号：US20090179787A1
公开(公告)日：2009-07-16
申请号：US12093565
申请日：2006-04-18
申请人： Junichi Naka , Koji Sushihara
发明人： Junichi Naka , Koji Sushihara
IPC分类号： H03M1/12 , H03K5/22
CPC分类号： H03M1/0607 , H03K5/2481 , H03M1/204 , H03M1/362
摘要： A comparator used in a parallel-type A/D converter, wherein a comparator 100 includes reset transistors mra and mrb. When the comparator 100 is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparator 100 is in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.
摘要翻译：一种用于并行型A / D转换器的比较器，其中比较器100包括复位晶体管mra和mrb。当比较器100处于复位状态时，将时钟信号的反相信号/ CLK提供给PMOS复位晶体管mra和mrb，以便将两个作为差分对的内部节点Va和Vb的两个电压强制复位到复位晶体管mra和mrb的预定复位电压。以预定的延迟产生时钟信号的反相信号/ CLK。因此，当比较器100处于复位状态时，消除内部节点Va和Vb的复位的时间点比比较器执行比较操作的时间延迟。因此，即使时钟信号的频率和模拟输入信号的频率高，形成差分对的内部节点的电压在比较器处于复位状态时也是平衡的，从而提高电压比较精度。

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