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21. 发明授权

US08363449B2 Floating source line architecture for non-volatile memory 有权
标题翻译：用于非易失性存储器的浮动源线架构
公开(公告)号：US08363449B2
公开(公告)日：2013-01-29
申请号：US13206550
申请日：2011-08-10
申请人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C7/12 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C13/0069
摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an STRAM memory cell or an RRAM memory cell. In some embodiments, a plurality of N non-volatile memory cells, where N is a greater than two, are connected to a common floating source line. A write circuit is adapted to program a selected memory cell of the plurality to a selected data state by passing a write current of selected magnitude through the selected memory cell and concurrently passing a portion of the write current in parallel through each of the remaining N−1 memory cells of the plurality via the common floating source line.
摘要翻译：用于将数据写入诸如STRAM存储器单元或RRAM存储器单元的非易失性存储单元的方法和装置。在一些实施例中，其中N大于2的多个N个非易失性存储器单元连接到公共的浮动源线。写入电路适于通过将所选择的大小的写入电流通过所选择的存储器单元来编程所选择的数据状态的所选择的存储单元，并且并行地通过所述剩余的N- 1个存储单元经由公共浮动源线。

22. 发明授权

US08154914B2 Predictive thermal preconditioning and timing control for non-volatile memory cells 有权
标题翻译：非易失性存储单元的预测性热预处理和时序控制
公开(公告)号：US08154914B2
公开(公告)日：2012-04-10
申请号：US13016390
申请日：2011-01-28
申请人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
发明人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
IPC分类号： G11C11/02 , G11C7/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.
摘要翻译：一种使用热预处理来将数据写入诸如自旋转矩传递随机存取存储器（STRAM）存储器单元的非易失性存储单元的方法和装置。在一些实施例中，将逻辑状态写入与第一块地址相关联的无条件非易失性第一存储器单元。热预处理同时应用于与响应于第一块地址选择的第二块地址相关联的非易失性第二存储器单元。

23. 发明授权

US08004872B2 Floating source line architecture for non-volatile memory 有权
标题翻译：用于非易失性存储器的浮动源线架构
公开(公告)号：US08004872B2
公开(公告)日：2011-08-23
申请号：US12272507
申请日：2008-11-17
申请人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/10
CPC分类号： G11C13/0002 , G11C7/12 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C13/0069
摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.
摘要翻译：一种将数据写入诸如RRAM存储单元的非易失性存储单元的方法和装置。在一些实施例中，非易失性存储单元的半导体阵列包括电阻感测元件（RSE）和开关器件。多个存储单元的RSE连接到位线，而多个存储单元的开关器件连接到字线并被操作以选择存储器单元。源极线连接到开关器件，并将一系列存储器单元连接在一起。此外，驱动器电路连接到位线，并且通过使写入电流沿着通过所选择的RSE的写入电流路径并且通过至少一部分所述选择的RSE而将所选择的源极线的选定RSE写入所选择的电阻状态剩余的RSE连接到所选择的源线。

24. 发明申请

US20110194337A1 Non-Volatile Memory Cell With Precessional Switching 有权
标题翻译：具有进动切换的非易失性存储单元
公开(公告)号：US20110194337A1
公开(公告)日：2011-08-11
申请号：US13091372
申请日：2011-04-21
申请人： Xiaobin Wang , Yong Lu , Haiwen Xi , Yuankai Zheng , Yiran Chen , Harry Hongyue Liu , Dimitar Dimitrov , Wei Tian , Brian Seungwhan Lee
发明人： Xiaobin Wang , Yong Lu , Haiwen Xi , Yuankai Zheng , Yiran Chen , Harry Hongyue Liu , Dimitar Dimitrov , Wei Tian , Brian Seungwhan Lee
IPC分类号： G11C11/00
CPC分类号： H01F10/329 , B82Y25/00 , G06F7/588 , G11C11/161 , G11C11/1675 , G11C11/1677 , G11C11/1693 , H01F10/3254 , H01F10/3286
摘要： A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.
摘要翻译：一种将数据写入非易失性存储单元的方法和装置，例如自旋转矩传递随机存取存储器（STRAM）存储单元。在一些实施例中，通过将一系列不确定的写入脉冲施加到磁性隧道结构中来将所选择的电阻状态写入到所选择的电阻状态。

25. 发明申请

US20110128778A1 Predictive Thermal Preconditioning and Timing Control for Non-Volatile Memory Cells 有权
标题翻译：非易失性记忆体的预测热预处理和时序控制
公开(公告)号：US20110128778A1
公开(公告)日：2011-06-02
申请号：US13016390
申请日：2011-01-28
申请人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
发明人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
IPC分类号： G11C11/02 , G11C7/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.
摘要翻译：一种使用热预处理来将数据写入诸如自旋转矩传递随机存取存储器（STRAM）存储器单元的非易失性存储单元的方法和装置。在一些实施例中，将逻辑状态写入与第一块地址相关联的无条件非易失性第一存储器单元。热预处理同时应用于与响应于第一块地址选择的第二块地址相关联的非易失性第二存储器单元。

26. 发明授权

US07936592B2 Non-volatile memory cell with precessional switching 有权
标题翻译：具有进动切换的非易失性存储单元
公开(公告)号：US07936592B2
公开(公告)日：2011-05-03
申请号：US12364589
申请日：2009-02-03
申请人： Xiaobin Wang , Yong Lu , Haiwen Xi , Yuankai Zheng , Yiran Chen , Harry Hongyue Liu , Dimitar Dimitrov , Wei Tan , Brian Seungwhan Lee
发明人： Xiaobin Wang , Yong Lu , Haiwen Xi , Yuankai Zheng , Yiran Chen , Harry Hongyue Liu , Dimitar Dimitrov , Wei Tan , Brian Seungwhan Lee
IPC分类号： G11C11/00
CPC分类号： H01F10/329 , B82Y25/00 , G06F7/588 , G11C11/161 , G11C11/1675 , G11C11/1677 , G11C11/1693 , H01F10/3254 , H01F10/3286
摘要： A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.
摘要翻译：一种将数据写入非易失性存储单元的方法和装置，例如自旋转矩传递随机存取存储器（STRAM）存储单元。在一些实施例中，通过将一系列不确定的写入脉冲施加到磁性隧道结构中来将所选择的电阻状态写入到所选择的电阻状态。

27. 发明申请

US20110080782A1 WRITE CURRENT COMPENSATION USING WORD LINE BOOSTING CIRCUITRY 有权
公开(公告)号：US20110080782A1
公开(公告)日：2011-04-07
申请号：US12967743
申请日：2010-12-14
申请人： Hai Li , Yiran Chen , Harry Hongyue Liu , Henry Huang , Ran Wang
发明人： Hai Li , Yiran Chen , Harry Hongyue Liu , Henry Huang , Ran Wang
IPC分类号： G11C11/15
CPC分类号： G11C8/08 , G11C11/1659 , G11C11/1675 , G11C13/0028 , G11C13/0069 , G11C2013/0071
摘要： Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.

28. 发明授权

US07916528B2 Predictive thermal preconditioning and timing control for non-volatile memory cells 有权
标题翻译：非易失性存储单元的预测性热预处理和时序控制
公开(公告)号：US07916528B2
公开(公告)日：2011-03-29
申请号：US12414452
申请日：2009-03-30
申请人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
发明人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
IPC分类号： G11C11/14 , G11C8/00 , G11C7/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.
摘要翻译：一种使用热预处理来将数据写入诸如自旋转矩传递随机存取存储器（STRAM）存储器单元的非易失性存储单元的方法和装置。在一些实施例中，将逻辑状态写入与第一块地址相关联的无条件非易失性第一存储器单元。热预处理同时应用于与响应于第一块地址选择的第二块地址相关联的非易失性第二存储器单元。

29. 发明授权

US07894250B2 Stuck-at defect condition repair for a non-volatile memory cell 有权
公开(公告)号：US07894250B2
公开(公告)日：2011-02-22
申请号：US12405918
申请日：2009-03-17
申请人： Alan Xuguang Wang , Xiaobin Wang , Dimitar V. Dimitrov , Hai Li , Haiwen Xi , Harry Hongyue Liu
发明人： Alan Xuguang Wang , Xiaobin Wang , Dimitar V. Dimitrov , Hai Li , Haiwen Xi , Harry Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C11/1659 , G11C11/1675 , G11C11/1677 , G11C11/1695 , G11C11/1697
摘要： A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.

30. 发明申请

US20110029714A1 RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY 有权
标题翻译：具有部分块更新能力的电阻式感知存储器阵列
公开(公告)号：US20110029714A1
公开(公告)日：2011-02-03
申请号：US12904653
申请日：2010-10-14
申请人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li
发明人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li
IPC分类号： G06F12/00 , G11C11/21 , G11C11/16
CPC分类号： G11C8/12 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C13/0007 , G11C13/0069 , G11C2013/0088 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.
摘要翻译：本发明的各种实施例总体上涉及一种用于在诸如由STRAM或RRAM单元形成的电阻式感测存储器（RSM）阵列上执行部分块更新操作的方法和装置。 RSM阵列被布置成多小区块（扇区），每个块具有物理块地址（PBA）。第一组用户数据在第一PBA被写入所选择的块。通过在第二PBA将第二组用户数据写入第二块来执行部分块更新操作，第二组用户数据更新第一PBA中第一组用户数据的一部分。然后读取第一和第二块以检索第二组用户数据和第一组用户数据的剩余部分。

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