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21. 发明申请

US20130019085A1 Efficient Recombining for Dual Path Execution 审中-公开
标题翻译：双路执行的有效重组
公开(公告)号：US20130019085A1
公开(公告)日：2013-01-17
申请号：US13180634
申请日：2011-07-12
申请人： Harold W. Cain, III , David M. Daly , Michael C. Huang , Jose E. Moreira , IL Park
发明人： Harold W. Cain, III , David M. Daly , Michael C. Huang , Jose E. Moreira , IL Park
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3804 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3859 , G06F9/3861
摘要： A mechanism is provided for reducing a penalty for executing a correct branch of a branch instruction. An execution unit in a processor of a data processing system executes a first branch of the branch instruction from a main thread of a processor and executes a second branch of the branch instruction from an assist thread of the processor. The execution unit determines whether the main thread is a correct branch of the branch instruction or the assist thread is the correct branch of the branch instruction. Responsive to the assist thread being the correct branch of the branch instruction, the execution unit pauses execution of the branch instruction on both the main thread and the assist thread. The execution unit then properly inherits a context of the main thread in order that execution of the second branch may continue.
摘要翻译：提供了用于减少执行分支指令的正确分支的惩罚的机制。数据处理系统的处理器中的执行单元从处理器的主线程执行分支指令的第一分支，并从处理器的辅助线程执行分支指令的第二分支。执行单元确定主线程是否是分支指令的正确分支，或辅助线程是分支指令的正确分支。响应于辅助线程是分支指令的正确分支，执行单元暂停在主线程和辅助线程上执行分支指令。执行单元然后适当地继承主线程的上下文，以便第二分支的执行可以继续。

22. 发明申请

US20130019083A1 Redundant Transactional Memory 审中-公开
标题翻译：冗余事务记忆
公开(公告)号：US20130019083A1
公开(公告)日：2013-01-17
申请号：US13179672
申请日：2011-07-11
申请人： Harold W. Cain, III , David M. Daly , Kattamuri Ekanadham , Michael C. Huang , Jose E. Moreira , Mauricio J. Serrano
发明人： Harold W. Cain, III , David M. Daly , Kattamuri Ekanadham , Michael C. Huang , Jose E. Moreira , Mauricio J. Serrano
IPC分类号： G06F9/30
CPC分类号： G06F9/30087 , G06F9/3834 , G06F9/3842 , G06F11/1492 , G06F11/1629 , G06F2201/845
摘要： A mechanism is provided for redundant execution of a set of instructions. A redundant execution begin (rbegin) instruction to be executed by a first hardware thread on the first processor is identified in the set of instructions. The set of instructions immediately after the rbegin instruction are executed on the first hardware thread and on a second hardware thread. Responsive to both the first processor and the second processor ending execution of the set of instructions, responsive to a first set of cache lines in a first speculative store matching a second set of cache lines in a second speculative store, and responsive to a first set of register states in a first status register matching a second set of register states in a second status register, dirty lines in the first speculative store are committed thereby committing a redundant transaction state to an architectural state.
摘要翻译：提供了用于一组指令的冗余执行的机制。在该组指令中识别由第一处理器上的第一硬件线程执行的冗余执行开始（rbegin）指令。 rbegin指令之后的指令集在第一个硬件线程和第二个硬件线程上执行。响应于所述第一处理器和所述第二处理器结束所述指令集的执行，响应于在第二推测存储器中匹配第二组高速缓存行的第一推测存储器中的第一组高速缓存行，并响应于第一集合在与第二状态寄存器中的第二组寄存器状态匹配的第一状态寄存器中的寄存器状态被提交，从而将第一推测存储器中的脏线提交给架构状态的冗余事务状态。

23. 发明申请

US20110276762A1 COORDINATED WRITEBACK OF DIRTY CACHELINES 有权
标题翻译：协调写入的快速缓存
公开(公告)号：US20110276762A1
公开(公告)日：2011-11-10
申请号：US12775510
申请日：2010-05-07
申请人： DAVID M. DALY , BENJIMAN L. GOODMAN , HILLERY C. HUNTER , WILLIAM J. STARKE , JEFFREY A. STUECHELI
发明人： DAVID M. DALY , BENJIMAN L. GOODMAN , HILLERY C. HUNTER , WILLIAM J. STARKE , JEFFREY A. STUECHELI
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0804 , G06F12/0817 , G06F12/0897 , Y02D10/13
摘要： A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue.
摘要翻译：数据处理系统包括处理器核心和耦合到处理器核心的高速缓存存储器层级。高速缓存存储器层级包括至少一个上级高速缓存和最低级高速缓存。存储器控制器耦合到最低级缓存和系统存储器，并且包括物理写队列，存储器控制器从该物理写队列将数据写入系统存储器。存储器控制器启动对最低级高速缓存的访问以放置到物理写入队列中，所选择的高速缓存线具有空间局部性，其中数据存在于物理写入队列中。

24. 发明授权

US09311228B2 Power reduction in server memory system 有权
标题翻译：服务器内存系统功耗降低
公开(公告)号：US09311228B2
公开(公告)日：2016-04-12
申请号：US13439457
申请日：2012-04-04
申请人： David M. Daly , Tejas Karkhanis , Valentina Salapura
发明人： David M. Daly , Tejas Karkhanis , Valentina Salapura
IPC分类号： G06F12/00 , G06F12/02 , G06F11/34 , G06F12/06
CPC分类号： G06F12/023 , G06F11/3409 , G06F11/3471 , G06F12/06 , G06F2201/81 , G06F2201/88 , G06F2212/1028 , G06F2212/2532 , G06F2212/502 , Y02D10/13 , Y02D10/34
摘要： A system and method for reducing power consumption of memory chips outside of a host processor device inoperative communication with the memory chips via a memory controller. The memory can operate in modes, such that via the memory controller, the stored data can be localized and moved at various granularities, among ranks established in the chips, to result in fewer operating ranks. Memory chips may then be turned on and off based on host memory access usage levels at each rank in the chip. Host memory access usage levels at each rank in the chip is tracked by performance counters established for association with each rank of a memory chip. Turning on and off of the memory chips is based on a mapping maintained between ranks and address locations corresponding to sub-sections within each rank receiving the host processor access requests.
摘要翻译：一种用于降低主处理器设备外部的存储器芯片的功耗的系统和方法，其经由存储器控制器与存储器芯片无效通信。存储器可以以模式操作，使得经由存储器控制器，存储的数据可以在芯片中建立的等级之间以各种粒度进行本地化和移动，从而导致更少的操作等级。然后可以基于芯片中每个级别的主机存储器访问使用级别来打开和关闭存储器芯片。芯片中每个级别的主机存储器访问使用级别由建立用于与存储器芯片的每个等级相关联的性能计数器跟踪。存储器芯片的导通和关闭是基于维持在对应于接收主机处理器访问请求的每个等级内的子部分的地址位置的地址位置之间的映射。

25. 发明授权

US08930625B2 Weighted history allocation predictor algorithm in a hybrid cache 有权
标题翻译：混合高速缓存中加权历史分配预测算法
公开(公告)号：US08930625B2
公开(公告)日：2015-01-06
申请号：US13611614
申请日：2012-09-12
申请人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/122 , G06F12/0897 , G06F12/121
摘要： A mechanism is provided for weighted history allocation prediction. For each member in a plurality of members in a lower level cache, an associated reference counter is initialized to an initial value based on an operation type that caused data to be allocated to a member location of the member. For each access to the member in the lower level cache, the associated reference counter is incremented. Responsive to a new allocation of data to the lower level cache and responsive to the new allocation of data requiring the victimization of another member in the lower level cache, a member of the lower level cache is identified that has a lowest reference count value in its associated reference counter. The member with the lowest reference count value in its associated reference counter is then evicted.
摘要翻译：提供了一种用于加权历史分配预测的机制。对于较低级缓存中的多个成员中的每个成员，相关联的引用计数器基于导致数据被分配给成员的成员位置的操作类型被初始化为初始值。对于对较低级缓存中的成员的每次访问，相关联的引用计数器递增。响应于对低级缓存的新数据分配并响应于需要在较低级别高速缓存中另一成员受害的数据的新分配，识别出在其级别缓存中具有最低参考计数值的成员相关参考计数器。然后将其相关参考计数器中具有最低参考计数值的成员逐出。

26. 发明授权

US08843707B2 Dynamic inclusive policy in a hybrid cache hierarchy using bandwidth 有权
标题翻译：使用带宽的混合缓存层次结构中的动态包容性策略
公开(公告)号：US08843707B2
公开(公告)日：2014-09-23
申请号：US13315395
申请日：2011-12-09
申请人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
IPC分类号： G06F13/00
CPC分类号： G06F12/0897 , G06F2212/502
摘要： A mechanism is provided for dynamic cache allocation using bandwidth. A bandwidth between a higher level cache and a lower level cache is monitored. Responsive to bandwidth usage between the higher level cache and the lower level cache being below a predetermined low bandwidth threshold, the higher level cache and the lower level cache are set to operate in accordance with a first allocation policy. Responsive to bandwidth usage between the higher level cache and the lower level cache being above a predetermined high bandwidth threshold, the higher level cache and the lower level cache are set to operate in accordance with a second allocation policy.
摘要翻译：提供了一种使用带宽进行动态高速缓存分配的机制。监视高级缓存和较低级别缓存之间的带宽。响应于较高级别高速缓存和较低级别高速缓存之间的带宽使用低于预定低带宽阈值，高级缓存和下级高速缓存被设置为根据第一分配策略进行操作。响应于高级缓存和低级高速缓存之间的带宽使用高于预定高带宽阈值，高级缓存和下级高速缓存被设置为根据第二分配策略进行操作。

27. 发明申请

US20140063983A1 Error Detection And Correction In A Memory System 审中-公开
标题翻译：内存系统中的错误检测和纠正
公开(公告)号：US20140063983A1
公开(公告)日：2014-03-06
申请号：US13605041
申请日：2012-09-06
申请人： David M. Daly
发明人： David M. Daly
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G06F11/1076 , G06F2211/1088 , G11C2029/0411 , G11C2211/4062
摘要： A method including providing a plurality of random access memories having at least a first region, a second region and a third region; storing protected data on the first region on at least two of the random access memories, where the protected data is stored distributed among the at least two random access memories of the first region; storing parity information for the protected data on the second region on at least a third one of the random access memories; and storing unprotected data on the third region.
摘要翻译：一种方法，包括提供具有至少第一区域，第二区域和第三区域的多个随机存取存储器; 将保护的数据存储在所述随机存取存储器中的至少两个上的第一区域上，其中所述受保护数据被存储在所述第一区域的所述至少两个随机存取存储器中; 将所述受保护数据的奇偶校验信息存储在所述随机存取存储器中的至少三分之一上的所述第二区域上; 并在第三区域上存储未受保护的数据。

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