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21. 发明申请

WO2013066572A2 REMOTE DIRECT MEMORY ACCESS ADAPTER STATE MIGRATION IN A VIRTUAL ENVIRONMENT 审中-公开
标题翻译：虚拟环境中的远程直接内存访问适配器状态迁移
公开(公告)号：WO2013066572A2
公开(公告)日：2013-05-10
申请号：PCT/US2012/059241
申请日：2012-10-08
申请人： INTEL CORPORATION , SHARP, Robert O. , KEELS, Kenneth G.
发明人： SHARP, Robert O. , KEELS, Kenneth G.
CPC分类号： G06F15/17331 , G06F3/0619 , G06F3/0644 , G06F3/065 , G06F3/067 , G06F9/45558 , G06F9/5016 , G06F2009/4557
摘要： In an embodiment of the present invention, a method includes partitioning a plurality of remote direct memory access context objects among a plurality of virtual functions, establishing a remote direct memory access connection between a first of the plurality of virtual functions, and migrating the remote direct memory access connection from the first of the plurality of virtual functions to a second of the plurality of virtual functions without disconnecting from the remote peer.
摘要翻译：在本发明的一个实施例中，一种方法包括在多个虚拟功能之间划分多个远程直接存储器访问上下文对象，在多个虚拟功能中的第一个之间建立远程直接存储器访问连接，以及迁移远程直接从所述多个虚拟功能中的第一个到所述多个虚拟功能中的第二虚拟功能的存储器访问连接，而不断开与所述远程对等体的连接。

22. 发明申请

WO2007022119A2 METHOD FOR SIMULATING A RESPONSE TO A STIMULUS 审中-公开
标题翻译：模拟对刺激反应的方法
公开(公告)号：WO2007022119A2
公开(公告)日：2007-02-22
申请号：PCT/US2006/031714
申请日：2006-08-15
申请人： THOMMES FAMILY, LLC , THOMMES, Glen, A. , THOMMES, Jeffrey, L.
发明人： THOMMES, Glen, A. , THOMMES, Jeffrey, L.
IPC分类号： G06F15/00
CPC分类号： G06F17/5009 , G05B17/02
摘要： A method of simulating a response to a stimulus is disclosed. In one embodiment, the method includes modeling the response with at least one differential equation, and executing instructions on a machine to numerically integrate the differential equation. The differential equation includes a parameter that depends on the fraction of the response that has occurred.
摘要翻译：公开了一种模拟刺激响应的方法。在一个实施例中，该方法包括用至少一个微分方程对响应进行建模，以及在机器上执行指令以对微分方程进行数值积分。微分方程包括一个取决于发生的响应分数的参数。

23. 发明申请

WO2022139931A1 DYNAMIC MITIGATION OF SPECULATION VULNERABILITIES 审中-公开
公开(公告)号：WO2022139931A1
公开(公告)日：2022-06-30
申请号：PCT/US2021/052108
申请日：2021-09-25
申请人： INTEL CORPORATION
发明人： WINTERTON, Richard , HAGHIGHAT, Mohammad Reza , MALLICK, Asit , ALAMELDEEN, Alaa , BASAK, Abhishek , BRANDT, Jason W. , CHYNOWETH, Michael , ROZAS, Carlos , CONSTABLE, Scott , DIXON, Martin , FERNANDEZ, Matthew , LIU, Fangfei , MCKEEN, Francis , NUZMAN, Joseph , POKAM, Gilles , UNTERLUGGAUER, Thomas , ZOU, Xiang
IPC分类号： G06F21/78 , G06F21/71 , H04L9/08
摘要： Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a hybrid key generator and memory protection hardware. The hybrid key generator is to generate a hybrid key based on a public key and multiple process identifiers. Each of the process identifiers corresponds to one or more memory spaces in a memory. The memory protection hardware is to use the first hybrid key to protect to the memory spaces.

24. 发明申请

WO2022066349A1 MONITORING PERFORMANCE COST OF EVENTS 审中-公开
公开(公告)号：WO2022066349A1
公开(公告)日：2022-03-31
申请号：PCT/US2021/047591
申请日：2021-08-25
申请人： INTEL CORPORATION
发明人： YASIN, Ahmad
IPC分类号： G06F11/30 , G06F11/34
摘要： Embodiments are disclosed for monitoring processor performance, including cost of events. In an embodiment, a processor includes a first counter, a second counter, a handler circuit, and an enable circuit. The first counter is to count occurrences of an event in the processor and to overflow upon the count of occurrences reaching a specified value. The second counter to measure a performance cost of the event. The handler circuit to generate and an event sampling record. The record is to include at least one value reflecting the performance cost. The enable circuit is to enable the handler circuit to generate the record.

25. 发明申请

WO2019132976A1 UNIFIED ADDRESS TRANSLATION FOR VIRTUALIZATION OF INPUT/OUTPUT DEVICES 审中-公开
公开(公告)号：WO2019132976A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/068938
申请日：2017-12-29
申请人： INTEL CORPORATION
发明人： KAKAIYA, Utkarsh Y. , KUMAR, Sanjay , SANKARAN, Rajesh M. , LANTZ, Philip R. , RAJ, Ashok , TIAN, Kun
IPC分类号： G06F12/02
摘要： Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second- level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.

26. 发明申请

WO2018125501A1 APPARATUSES AND METHODS FOR MULTILANE UNIVERSAL SERIAL BUS (USB2) COMMUNICATION OVER EMBEDDED UNIVERSAL SERIAL BUS (eUSB2) 审中-公开
公开(公告)号：WO2018125501A1
公开(公告)日：2018-07-05
申请号：PCT/US2017/063931
申请日：2017-11-30
申请人： INTEL CORPORATION
发明人： SRIVASTAVA, Amit Kumar
IPC分类号： G06F13/38 , G06F13/42
CPC分类号： G06F13/4282 , G06F13/287 , G06F13/387 , G06F2213/0026 , G06F2213/4002 , Y02D10/14 , Y02D10/151
摘要： Methods and apparatuses relating to circuitry for multilane serial bus communications are described. In an embodiment, an apparatus includes a serial bus controller, upstream serial bus lanes, a single downstream serial bus lane, and a host/device lane controller. The serial bus controller is to send and receive data transmissions to and from serial bus devices. The upstream serial bus lanes correspond to the serial bus devices and are associated with serial port addresses. The host/device lane controller is to receive data transmissions through the upstream serial bus lanes and includes a port address assignment circuit and a multiplexer. The port address assignment circuit is to assign serial port addresses to data transmissions, to be included in data transmissions to identify the upstream serial bus lanes through which the data transmission was received. The multiplexer is to forward data transmissions from upstream serial bus lanes to the downstream serial bus lane.

27. 发明申请

WO2017023434A1 SECURE INPUT/OUTPUT DEVICE MANAGEMENT 审中-公开
标题翻译：安全输入/输出设备管理
公开(公告)号：WO2017023434A1
公开(公告)日：2017-02-09
申请号：PCT/US2016/038378
申请日：2016-06-20
申请人： INTEL CORPORATION
发明人： McGOWAN, Steven B.
IPC分类号： G06F21/82 , G06F21/60 , G06F13/40
CPC分类号： G06F21/602 , G06F13/28 , G06F13/4068 , G06F13/4282 , G06F21/57
摘要： Embodiments of apparatus and methods for secure I/O device management are disclosed. In an embodiment, an apparatus includes a processor and an I/O controller. The processor has secure execution environment support, wherein the processor is to establish a secure execution environment using the secure execution environment support. The I/O controller includes an integrated trusted I/O device, wherein the trusted I/O device is to receive an unencrypted request to configure the trusted I/O device via a default control endpoint of the trusted I/O device, configure a command endpoint and a response endpoint in response to receipt of the unencrypted request, receive an encrypted command from the secure execution environment via the command endpoint, perform a device management operation related to the I/O controller in response to receipt of the encrypted command, and transmit an encrypted response to the secure execution environment via the response endpoint in response to performance of the device management operation.
摘要翻译：公开了用于安全I / O设备管理的装置和方法的实施例。在一个实施例中，装置包括处理器和I / O控制器。处理器具有安全的执行环境支持，其中处理器将使用安全执行环境支持建立安全的执行环境。所述I / O控制器包括集成的可信I / O设备，其中所述可信I / O设备将通过所述可信I / O设备的默认控制端点接收未加密的请求以配置所述可信I / O设备，响应于接收到未加密请求的命令端点和响应端点，经由命令端点从安全执行环境接收加密命令，响应于接收到加密命令执行与I / O控制器相关的设备管理操作，以及响应于所述设备管理操作的执行，经由所述响应端点向所述安全执行环境发送加密的响应。

28. 发明申请

WO2016153675A1 CUSTOM PROTECTION AGAINST SIDE CHANNEL ATTACKS 审中-公开
标题翻译：定制防范侧面通道攻击
公开(公告)号：WO2016153675A1
公开(公告)日：2016-09-29
申请号：PCT/US2016/019019
申请日：2016-02-23
申请人： INTEL CORPORATION
发明人： CAPRIOLI, Paul
IPC分类号： G06F21/56 , G06F21/55 , H04L9/00
CPC分类号： H04L63/1416 , G06F21/125 , G06F21/556 , G06F21/60 , G06F21/71 , G06F21/72 , H04L9/003 , H04L63/1441 , H04L63/162
摘要： Embodiments of an invention for custom protection against side channel attacks are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive an instruction to provide for shielding code against side channel attacks, wherein the instruction includes a first operand to specify one of a plurality of levels of protection. The execution hardware is to execute the instruction, wherein execution of the instruction includes configuring the processor to provide a specified level of protection.
摘要翻译：公开了用于针对侧面信道攻击的定制保护的发明的实施例。在一个实施例中，处理器包括指令硬件和执行硬件。指令硬件是接收指令以提供针对侧信道攻击的屏蔽码，其中该指令包括指定多个保护级别之一的第一操作数。执行硬件是执行指令，其中指令的执行包括配置处理器以提供指定级别的保护。

29. 发明申请

WO2016060859A1 AN INTERFACE BETWEEN A DEVICE AND A SECURE PROCESSING ENVIRONMENT 审中-公开
标题翻译：设备之间的界面和安全的处理环境
公开(公告)号：WO2016060859A1
公开(公告)日：2016-04-21
申请号：PCT/US2015/053526
申请日：2015-10-01
申请人： INTEL CORPORATION
发明人： NARENDRA TRIVEDI, Alpa , CHHABRA, Siddhartha , KANG, Xiaozhu , DEWAN, Prashant , SAVAGAONKAR, Uday , DURHAM, David
IPC分类号： G06F21/53
CPC分类号： G06F21/53 , G06F2221/033
摘要： Embodiments of an invention for an interface between a device and a secure processing environment are disclosed. In one embodiment, a system includes a processor, a device, and an interface plug-in. The processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to create a secure processing environment. The execution unit is to execute an application in the secure processing environment. The device is to execute a workload for the application. The interface plug-in is to provide an interface for the device to enter the secure processing environment to execute the workload.
摘要翻译：公开了用于设备和安全处理环境之间的接口的发明的实施例。在一个实施例中，系统包括处理器，设备和接口插件。处理器包括指令单元和执行单元。指令单元将接收创建安全处理环境的指令。执行单元在安全处理环境中执行应用。该设备将为应用程序执行工作负载。接口插件是为设备提供一个接口，进入安全处理环境以执行工作负载。

30. 发明申请

WO2014105158A1 SIGNALING SOFTWARE RECOVERABLE ERRORS 审中-公开
标题翻译：信号软件可恢复的错误
公开(公告)号：WO2014105158A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/047311
申请日：2013-06-24
申请人： INTEL CORPORATION , RAJ, Ashok , HOLM, John G. , NEIGER, Gilbert , SANKARAN, Rajesh M. , KUMAR, Mohan J.
发明人： RAJ, Ashok , HOLM, John G. , NEIGER, Gilbert , SANKARAN, Rajesh M. , KUMAR, Mohan J.
IPC分类号： G06F11/00
CPC分类号： G06F11/006 , G06F11/0715 , G06F11/0772 , G06F11/0793
摘要： Embodiments of an invention for signaling software recoverable errors are disclosed. In one embodiment, a processor includes a first unit, a programmable indicator, and a second unit. The first unit is to detect a poison error. The programmable indicator is to indicate whether the poison error is signaled as a machine check error or as one of a fault and a system management interrupt. The second unit is to signal the poison error as one of a fault and a system management error responsive to the programmable indicator.
摘要翻译：公开了用于信令软件可恢复错误的发明的实施例。在一个实施例中，处理器包括第一单元，可编程指示器和第二单元。第一个单位是检测毒物的错误。可编程指示灯是指示是否发出毒物误差作为机器检查错误或作为故障和系统管理中断之一发出信号。第二个单元将响应于可编程指示器的毒性错误信号作为故障之一和系统管理错误。

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