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21. 发明授权

EP1324619B1 All-digital clock recovery using a fractional divider 有权
$All-digital clock recovery using a fractional divider$
标题翻译：全数字时钟恢复与分数分频器比率
公开(公告)号：EP1324619B1
公开(公告)日：2006-05-17
申请号：EP02022752.6
申请日：2002-10-11
申请人： STMicroelectronics Pvt. Ltd
发明人： Chakravarthy, Kalyana, Flat No. 7
IPC分类号： H04N7/62 , H04N7/56 , H03L7/197 , H04N5/12 , H03L7/00
CPC分类号： H04N21/4305 , H03L7/0992 , H03L7/181

22. 发明公开

EP1492234A3 Power on reset circuit 审中-公开
标题翻译：上电复位电路
公开(公告)号：EP1492234A3
公开(公告)日：2006-03-15
申请号：EP04014644.1
申请日：2004-06-22
申请人： STMicroelectronics Pvt. Ltd
发明人： Roy, Amit
IPC分类号： H03K17/22
CPC分类号： H03K17/223 , H03K2217/0036
摘要： The present invention provides an improved Power-On-reset (POR) circuit providing enhanced reliability and automatic power-down capability, comprising a supply voltage sensing circuit (IS1,P1,VCCS), a delay element (1) connected to the output of the supply voltage sensing circuit, and a switch (P2,N2) that activates the output POR signal when the output of the delay element indicates a reduced supply voltage and deactivates the POR output and provides feedback to reduce current through the supply voltage sensing circuit once the supply voltage is normal.

23. 发明公开

EP1630958A2 A minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry 有权
标题翻译：一个Polyphaseninterpolationsfilters的使用所述系数对称性以集成电路的最小空间要求执行
公开(公告)号：EP1630958A2
公开(公告)日：2006-03-01
申请号：EP05018679.0
申请日：2005-08-29
申请人： STMicroelectronics Pvt. Ltd
发明人： Bhuvanagiri, Aditha , Singh, Halvinder , Malik, Rakesh
IPC分类号： H03H17/06
CPC分类号： H03H17/0275 , H03H17/0657
摘要： A minimal area integrated circuit implementation of a polyphase interpolation filter using symmetry of coefficients for at least one channel of input data, comprising, an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a channel select multiplexer block selecting a channel in response to a first set of internal control signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals , an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block for synchronization of filtered signal, and a control block to generate clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware requirement of coefficient set implementation in a polyphase interpolation filter.
摘要翻译：的最小面积集成电路实施方式使用系数的输入数据的至少一个信道，在输入接口块，包括用于同步输入信号到第一内部时钟信号的对称性的多相内插滤波器的; 用于提供多延迟输出信号的存储器块; 一信道选择复用器块选择响应于第一组内部控制信号的信道; 用于输出铃声复用器输入接口块的信号，用于响应于第二组内部控制信号的生成镜像系数集合，用于产生镜像和/或对称的系数组的系数块，并且输出的过滤的多个选择的多个信号，以输出多路转换器块，用于执行选择，增益控制和数据宽度控制对所述多个经滤波的信号的输出寄存器块为滤波后的信号的同步，以及控制块，为实现滤波器的生成时钟信号，并延时之间两个信道来访问的一组系数，从而最小化在一多相内插滤波器系数集合执行硬件要求。

24. 发明公开

EP1538596A2 LCD driver with adjustable contrast 有权
标题翻译：安德森
公开(公告)号：EP1538596A2
公开(公告)日：2005-06-08
申请号：EP04028541.3
申请日：2004-12-02
申请人： STMicroelectronics Pvt. Ltd. , STMicroelectronics GmbH
发明人： Khurana, Jatin , Gourdou, Yvon
IPC分类号： G09G3/36
CPC分类号： G09G3/3622 , G09G3/18 , G09G3/2014 , G09G3/2018 , G09G3/3614 , G09G2310/06 , G09G2320/0204 , G09G2320/0626 , G09G2320/066
摘要： An LCD display driver providing adjustable contrast independently of multiplexing requirements by generating each COM signal in a time slot of a repeating signal frame, each COM signal containing one or more active periods and one or more inactive periods, the relative time proportions of which are adjustable, and corresponding SEGMENT signals turn on/off required segments while maintaining an essentially zero DC component, the logic levels and the relative active time and inactive times of the COM and segment signals being adjustable for increasing or decreasing the RMS voltage levels across the LCD element as desired.
摘要翻译：一种LCD显示驱动器，通过在重复信号帧的时隙中产生每个COM信号来提供独立于复用要求的可调对比度，每个COM信号包含一个或多个有效周期和一个或多个非活动时段，其相对时间比例可调，并且相应的SEGMENT信号打开/关闭所需的段，同时保持基本为零的DC分量，COM和段信号的逻辑电平和相对有效时间和无效时间是可调节的，用于增加或减少跨越LCD元件的RMS电压电平如预期的。

25. 发明公开

EP1416373A3 Method and apparatus to reduce access time in synchronous fifos with zero latency overhead 审中-公开
标题翻译：用于减少同步FIFO的存取时间无延迟成本的方法和装置
公开(公告)号：EP1416373A3
公开(公告)日：2005-01-05
申请号：EP03024591.4
申请日：2003-10-28
申请人： STMicroelectronics Pvt. Ltd
发明人： Chakravarthy, Kalyana , Verma, Jayesh
IPC分类号： G06F7/06
CPC分类号： G06F5/10
摘要： The method and apparatus reduce access time in synchronous FIFOs with zero latency overheads. A FIFO buffer comprises FIFO means (301) storing 'n' data words, each 'm' bits wide, having an 'm' bit wide data input terminal. Furthermore, the FIFO buffer includes read data set selection means (303) connected to the data output terminals of the FIFO means and having two data output terminals providing simultaneous access to a selected storage location at an odd address and an even address. Odd read pointer generating means (304) provide the selection input to the data selection means (303) for selecting data at an odd read address of the read data selection means, while even read pointer generating means (305) provide the input for selecting data at an even read address. Multiplexing means (306) coupled to each of the two data output terminals of the read data set selection means select one of its outputs as the final output of the FIFO. State controlling means (310) coupled to the multiplexing means (306) control the selection of the final output and the selection input to the read data set selection means for selecting an odd read address and an even read address.

26. 发明公开

EP1443645A3 Linearly scalable finite impulse response (FIR) filter 有权
标题翻译：线性缩放有限脉冲响应
公开(公告)号：EP1443645A3
公开(公告)日：2004-09-15
申请号：EP03104135.3
申请日：2003-11-10
申请人： STMicroelectronics Pvt. Ltd.
发明人： SAHA, Kaushik , MAITI, Srijib Narayan
IPC分类号： H03H17/06
CPC分类号： H03H17/0223 , H03H17/06 , H03H2017/0298
摘要： The present invention provides an improved Finite Impulse Response (FIR) filter providing linear scalability and implementation without the need for delay lines, comprising a multiprocessor architecture including a plurality of ALUs (Arithmetic and Logic Units), multipliers units, data cache, and load/store units sharing a common instruction cache, and multi-port memory, and an assigning means for assigning to each available processing unit the computation of specified unique partial product terms and the accumulation of each computed partial product on specified output sample values. A method is also provided for implementing an improved Finite Impulse Response (FIR) filter providing linear scalability using a multiprocessing architecture platform without the need for delay lines.

27. 发明公开

EP1443645A2 Linearly scalable finite impulse response (FIR) filter 有权
标题翻译：线性滑雪者过滤器
公开(公告)号：EP1443645A2
公开(公告)日：2004-08-04
申请号：EP03104135.3
申请日：2003-11-10
申请人： STMicroelectronics Pvt. Ltd.
发明人： SAHA, Kaushik , MAITI, Srijib Narayan
IPC分类号： H03H17/06
CPC分类号： H03H17/0223 , H03H17/06 , H03H2017/0298
摘要： The present invention provides an improved Finite Impulse Response (FIR) filter providing linear scalability and implementation without the need for delay lines, comprising a multiprocessor architecture including a plurality of ALUs (Arithmetic and Logic Units), multipliers units, data cache, and load/store units sharing a common instruction cache, and multi-port memory, and an assigning means for assigning to each available processing unit the computation of specified unique partial product terms and the accumulation of each computed partial product on specified output sample values. A method is also provided for implementing an improved Finite Impulse Response (FIR) filter providing linear scalability using a multiprocessing architecture platform without the need for delay lines.
摘要翻译：本发明提供了一种改进的有限脉冲响应（FIR）滤波器，其提供线性可扩展性和实现，而不需要延迟线，包括包括多个ALU（算术和逻辑单元），乘法器单元，数据高速缓存和负载/ 共享公共指令高速缓存的存储单元和多端口存储器，以及分配装置，用于向每个可用处理单元分配指定的唯一部分乘积项的计算以及每个计算的部分乘积在指定的输出样本值上的累积。还提供了一种用于实现改进的有限脉冲响应（FIR）滤波器的方法，其使用多处理架构平台提供线性可扩展性，而不需要延迟线。

28. 发明公开

EP1359588A2 Memory architecture for increased speed and reduced power consumption 审中-公开
标题翻译： Speicherarchitektur miterhöhterGeschwindigkeit und reduziertem Stromverbrauch
公开(公告)号：EP1359588A2
公开(公告)日：2003-11-05
申请号：EP03009612.7
申请日：2003-04-29
申请人： STMicroelectronics Pvt. Ltd
发明人： Nautiyal, Vivek , Kumar, Ashish
IPC分类号： G11C8/14
CPC分类号： G11C7/18 , G11C8/14
摘要： An improved multi-wordline memory architecture providing decreased bitline coupling for increased speed and reduced power consumption comprising an interleaving arrangement for connecting adjacent bitcells to different wordlines, coupled to a multiplexing arrangement for sharing bitlines of adjacent bitcells.
摘要翻译：一种改进的多字线存储器架构，其提供降低的位线耦合以提高速度和降低的功耗，包括用于将相邻位单元连接到不同字线的交错布置，耦合到用于共享相邻位单元的位线的复用布置。

29. 发明公开

EP1324619A2 An improved fractional divider 有权
$An improved fractional divider$
标题翻译：全数字时钟恢复与分数分频器比率
公开(公告)号：EP1324619A2
公开(公告)日：2003-07-02
申请号：EP02022752.6
申请日：2002-10-11
申请人： STMicroelectronics Pvt. Ltd
发明人： Chakravarthy, Kalyana, Flat No. 7
IPC分类号： H04N7/62 , H04N7/56 , H03L7/197 , H04N5/12
CPC分类号： H04N21/4305 , H03L7/0992 , H03L7/181
摘要： A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values (29) characterized in that controlled clock source means consists of controllable digital Fractional Divider means (2.5) receiving a control value from digital comparator means (2.3) and a clock input from a digital clock synthesizer means (2.8) driven by a fixed oscillator means (2.7).

30. 发明公开

EP3439313A1 DISTRIBUTED ENVIRONMENT MONITORING STATION INTERFACING WITH SATELLITE TV AND BROADBAND INTERNET 审中-公开
公开(公告)号：EP3439313A1
公开(公告)日：2019-02-06
申请号：EP17188533.8
申请日：2017-08-30
申请人： STMicroelectronics International N.V. , STMicroelectronics Pvt. Ltd.
发明人： DASGUPTA, Nabarun , CHATTERJEE, Subrata , SINGH, Hemendra , PATHAK, Amit Kumar
IPC分类号： H04N21/61 , H04N21/658 , H04N21/422 , G01W1/00
摘要： Disclosed herein is a system (e.g. satellite TV, satellite broadband) including a communications connection, with a set top box (58) coupled to the communications connection. A control unit (70) for a receiver (52) is coupled to the communications connection. At least one environmental sensor (51 a, 51b) is configured to generate environmental data about a local environment in which the at least one environmental sensor is located, and to send the environmental data to the control unit (70). The control unit (70) is configured to transmit the environmental data to the set top box over the communications connection. The set top box (58) is configured to process the environmental data. The set top box (58) may send the environmental data to a server f(62) or weather prediction, use in a community weather portal, etc.

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