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    • 27. 发明申请
    • RADIATION DETECTOR ARRAY USING RADIATION SENSITIVE BRIDGES
    • 使用辐射敏感桥梁的辐射探测器阵列
    • WO1990016082A1
    • 1990-12-27
    • PCT/US1990000525
    • 1990-01-30
    • HUGHES AIRCRAFT COMPANY
    • HUGHES AIRCRAFT COMPANYGRINBERG, JanWELKOWSKY, Murray, S.WU, Chiung-ShengBRAATZ, Paul, A.
    • H01L27/146
    • G01J5/10G01J5/20G01J5/22G01J5/522H01L27/1465
    • An infrared (IR) simulator is disclosed in which an array of pixels is defined on an insulative substrate by resistor bridges which contact the substrate at spaced locations and are separated from the substrate, and thereby thermally insulated therefrom, between the contact locations. Semiconductor drive circuits on the substrate enable desired current flows through the resistor bridges in response to input control signals, thereby establishing the appropriate IR radiation from each of the pixels. The drive circuits and also at least some of the electrical lead lines are preferably located under the resistor bridges. A thermal reflector below each bridge shields the drive circuit and reflects radiation to enhance the IR output. The drive circuits employ sample and hold circuits which produce a substantially flicker-free operation, whith the resistor bridges being impedance matched with their respective drive circuits. The resistor bridges may be formed by coating insulative base bridges with a resistive layer having the desired properties, and overcoating the resistive layers with a thermally emissive material. The array is preferably formed on a silicon-on-saphire (SOS) wafer. Arrays of electromagnetic radiation bridge detectors may also be formed, with the bridges having either resistor, thermocouple or Schottky junction constructions.
    • 公开了一种红外(IR)模拟器,其中像素阵列通过电阻器桥限定在绝缘衬底上,电阻器桥在间隔开的位置处接触衬底,并且在接触位置之间与衬底分离,从而与衬底隔离。 衬底上的半导体驱动电路响应于输入控制信号使期望的电流流过电阻器桥,从而从每个像素建立适当的红外辐射。 驱动电路以及至少一些电引线优选位于电阻桥下。 每个桥下的热反射器屏蔽驱动电路并反射辐射以增强IR输出。 驱动电路采用产生基本上无闪烁操作的采样和保持电路,因为电阻器桥与它们各自的驱动电路阻抗匹配。 可以通过用具有期望特性的电阻层涂覆绝缘基桥来形成电阻器桥,并用热发射材料覆盖电阻层。 该阵列优选形成在硅 - 硅膜(SOS)晶片上。 也可以形成电磁辐射桥接检测器阵列,其中桥具有电阻器,热电偶或肖特基结结构。
    • 28. 发明申请
    • STEREO SYNTHESIZER
    • 立体声合成器
    • WO1990011670A1
    • 1990-10-04
    • PCT/US1989001167
    • 1989-03-27
    • HUGHES AIRCRAFT COMPANY
    • HUGHES AIRCRAFT COMPANYKLAYMAN, Arnold, I.
    • H04S05/00
    • H04S5/00H04S1/002H04S1/005
    • A stereo image enhancement system, in which difference signal components in relatively quieter difference signal frequency bands are boosted to provide an improved stereo image, is provided with a stereo input that is synthetically derived from a monaural signal (L + R). Simulated sum (L + R)s and simulated difference (L - R)s signals are provided from a monaural input (L + R) by sending the input through a phase shifter and splitter (12) that provides 0° and 90° outputs with a constant 90° phase separation between the two at all audio frequencies. The leading one of the two output signals from the phase shifter is employed as a simulated sum signal, and the other as a simulated difference signal. The simulated difference signal has different frequency components, each delayed by different amounts relative to corresponding components of like frequency of the simulated sum signal. This provides an effective synthetic difference signal, with both sum and difference signals being suitably filtered to provide an improved pair of synthetically derived stereo sum and difference signals (L + R)s, (L - R)s as inputs to an image enhancement circuit.
    • 30. 发明申请
    • LOW TEMPERATURE COFIRED CERAMIC PACKAGES FOR MICROWAVE AND MILLIMETER WAVE GALLIUM ARSENIDE INTEGRATED CIRCUITS
    • 用于微波和微波炉的低温辅助陶瓷包装阿塞拜疆一体化电路
    • WO1990007793A1
    • 1990-07-12
    • PCT/US1989005026
    • 1989-11-13
    • HUGHES AIRCRAFT COMPANY
    • HUGHES AIRCRAFT COMPANYPOLINSKI, Paul, W., Sr.
    • H01L23/66
    • H01L23/66H01L2924/0002H01L2924/09701H01L2924/3011H01P3/08H05K1/183H01L2924/00
    • A low temperature cofired monolithic ceramic package (10) for use with microwave and millimeter wave gallium arsenide integrated circuits, or the like. In situ buried passive components (22), including capacitors, resistors, couplers and inductors are incorporated within a cofired substrate structure (12). Fields of interconnected staggered or stacked vias (56, 58) are provided in the substrate below the integrated circuit for efficient heat transfer and electrical connection to a ground plane (20) that eliminates complicated heat sink structures. At least one cavity (24) is provided in the top surface to confine integrated circuit chips (28). A plurality of connectable electrical conductors (34, 36, 38, 40, 42) including RF input and output leads and DC bias leads for the chip extend from the edge of the substrate (12) to the edge of the cavity (24). A sidewall (14) is extended around the periphery of the cavity (24) and comprises a low temperature cofired structure which is cofired with the substrate (12). The sidewall (14) has a metallized top surface and interconnected metallization and vias extending from the top surface to the top surface layer of the substrate (12). A cover (16) is provided which is attachable to the metallized top surface of the sidewall (14). The electrical and thermal interconnections provided in the sidewall (14) and substrate (12) are provided by means of the plurality of interconnected staggered or stacked via interconnects. Electrical and thermal integrity is achieved which permits dissipation of heat by way of the ground plane and top cover, and electrical shielding is achieved by interconnecting the conductive components.