专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US5859571A Frequency trimmable oscillator and frequency multiplier 失效
标题翻译：频率可调振荡器和倍频器
公开(公告)号：US5859571A
公开(公告)日：1999-01-12
申请号：US814913
申请日：1997-03-11
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C11/56 , G11C16/14 , G11C16/16 , H03K3/0231 , H03B19/14 , H03K3/354
CPC分类号： H03K3/0231 , G11C11/5628 , G11C11/5635 , G11C16/14 , G11C16/16 , G11C2211/5645
摘要： A pure MOS-implementable oscillator requires no trimming to make the oscillation frequency Vdd independent, but permits trimming to compensate for process and fabrication variations. A current generator creates a core reference current Iosc0, mirrored programmable trim currents, and dynamic reference voltages that do not require a constant Vdd source. A programmable delay unit provides value-programmable capacitors that receive mirrored currents A.times.(M/N).times.Iosc0, where A is a MOS channel W/L ratio constant, and M and N are integers. The currents create ramp-like voltage signals across the capacitors, the slewrate being A.times.(M/N).times.Iosc0/capacitance. A comparator unit compares the ramp-like signals, which ramp-down from Vdd, against a (Vdd-Vt) reference voltage (Vt being a MOS threshold voltage). The comparator unit outputs complementary signals that toggle a set-reset flipflop, whose output is the oscillator output signal. This signal is fedback to the programmable delay unit to toggle on and off the current flow that determines oscillation period. Frequency change due to discrepancies between anticipated and realized load resistors and capacitors may be coarse and/or fine trimmed, for example by incrementally varying M and/or by turning-on a current-providing MOS device having an appropriate W/L value for A. The oscillator includes two programmable delay paths and can accept an input oscillator signal and output a signal whose frequency is a non-integer or integer multiple, simply by varying capacitor ratios.
摘要翻译：纯MOS可实现的振荡器不需要修整以使振荡频率Vdd独立，但允许修整以补偿工艺和制造变化。电流发生器产生核心参考电流Iosc0，镜像可编程微调电流和不需要恒定Vdd源的动态参考电压。可编程延迟单元提供接收镜像电流Ax（M / N）xIosc0的值可编程电容器，其中A是MOS通道W / L比常数，M和N是整数。电流在电容器两端产生斜坡状电压信号，摆率为Ax（M / N）xIosc0 /电容。比较器单元将从Vdd斜降的斜坡信号与（Vdd-Vt）参考电压（Vt为MOS阈值电压）进行比较。比较器单元输出互补信号，其触发设置复位触发器，其输出是振荡器输出信号。该信号被反馈到可编程延迟单元以打开和关闭确定振荡周期的电流。由于预期和实现的负载电阻器和电容器之间的差异导致的频率变化可以是粗略和/或微调，例如通过逐渐改变M和/或通过接通具有适当W / L值的电流提供MOS器件该振荡器包括两个可编程延迟路径，并且可以简单地通过改变电容器比率来接受输入振荡器信号并输出频率为非整数或整数倍的信号。

22. 发明授权

US5856942A Flash memory array and decoding architecture 失效
标题翻译：闪存阵列和解码架构
公开(公告)号：US5856942A
公开(公告)日：1999-01-05
申请号：US884926
申请日：1997-06-30
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C11/56 , G11C16/08 , G11C16/14 , G11C16/16 , G11C16/30 , G11C16/34 , H01L27/115 , G11C11/34
CPC分类号： G11C16/3427 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/14 , G11C16/16 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3418 , G11C16/3431 , G11C16/3445 , H01L27/115 , G11C2211/5621 , G11C8/14
摘要： A flash memory circuit having a word line decoder with even and odd word line latches and a source line decoder with a source line latch is disclosed. The word line decoders and source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.
摘要翻译：具有具有偶数和奇数字线锁存器的字线解码器和具有源极线锁存器的源极线解码器的闪存电路被公开。字线解码器和源极线解码器提供同时擦除闪存中两个相邻字线的存储单元的能力，并逐字地验证存储单元字。通过同时擦除两个相邻行，本发明的实施例消除了与常规闪存电路相关的过度擦除和源干扰问题。解码架构提供了可以从一对到大量多对字线的灵活的擦除大小。通过将字线的存储单元划分成多个段，解码电路还提供选择用于擦除的字线段的存储单元的能力。

23. 发明授权

US5777924A Flash memory array and decoding architecture 失效
标题翻译：闪存阵列和解码架构
公开(公告)号：US5777924A
公开(公告)日：1998-07-07
申请号：US872475
申请日：1997-06-05
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C11/56 , G11C16/08 , G11C16/14 , G11C16/16 , G11C16/30 , G11C16/34 , H01L27/115 , G11C11/34 , G11C7/00
CPC分类号： G11C16/3427 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/14 , G11C16/16 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3418 , G11C16/3431 , G11C16/3445 , H01L27/115 , G11C2211/5621 , G11C8/14
摘要： A flash memory circuit having a word line decoder with even and odd word line latches and a source line decoder with a source line latch is disclosed. The word line decoders and source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminates over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.
摘要翻译：具有具有偶数和奇数字线锁存器的字线解码器和具有源极线锁存器的源极线解码器的闪存电路被公开。字线解码器和源极线解码器提供同时擦除闪存中两个相邻字线的存储单元的能力，并逐字地验证存储单元字。通过同时擦除两个相邻行，本发明的实施例消除了与常规闪存电路相关联的过度擦除和源干扰问题。解码架构提供了可以从一对到大量多对字线的灵活的擦除大小。通过将字线的存储单元划分成多个段，解码电路还提供选择用于擦除的字线段的存储单元的能力。

24. 发明授权

US5600586A Flat-cell ROM and decoder 失效
标题翻译：平板ROM和解码器
公开(公告)号：US5600586A
公开(公告)日：1997-02-04
申请号：US279682
申请日：1994-07-25
申请人： Peter W. Lee
发明人： Peter W. Lee
IPC分类号： H01L27/112 , G11C17/12 , H01L21/8246 , G11C17/00
CPC分类号： G11C17/126
摘要： A flat-cell ROM array includes a bank of field effect transistors, each having a source, drain and gate, formed by ion implantation between columns of buried N+ and under rows of polysilicon, wherein adjacent columns of buried N+ are the source and drain of at least one transistor and a corresponding row of polysilicon is the gate of the transistor. Each of these transistors is programmed to have one of a plurality of threshold voltages depending on a desired storage value. Attached to the bank of transistors is an upper selector network associated with the bank connected to a first class of alternating sets of the columns, and a lower selector network associated with the bank connected to a second class of alternating sets of the columns. A method provides steps for performing the present invention.
摘要翻译：平面单元ROM阵列包括一组场效应晶体管，每一个具有源极，漏极和栅极，通过离子注入在掩埋N +的列之间和下行多晶硅之间形成，其中相邻的掩埋N +列是源极和漏极至少一个晶体管和对应的多晶硅行是晶体管的栅极。根据期望的存储值，将这些晶体管中的每一个编程为具有多个阈值电压中的一个。连接到晶体管组的是与连接到第一类交替列列的存储体相关联的上选择器网络，以及与连接到第二类交替列列的存储体相关联的下选择器网络。一种方法提供了执行本发明的步骤。

25. 发明授权

US5777923A Flash memory read/write controller 失效
标题翻译：闪存读/写控制器
公开(公告)号：US5777923A
公开(公告)日：1998-07-07
申请号：US664639
申请日：1996-06-17
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/16 , G11C16/26 , H01L27/115 , G11C11/34
CPC分类号： G11C16/3418 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3413 , G11C16/3431 , G11C8/08 , H01L27/115 , G11C16/08 , G11C16/24 , G11C2211/5644 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： A flash memory includes a flash transistor array, a wordline decoder, a bitline decoder, a sourceline decoder and a read/write controller. The read/write controller has a voltage terminal to receive an input voltage and a data terminal to receive a new data signal. A sense amplifier is coupled to the bitline decoder and configured to sense a signal on a selected bitline and to generate an internal old data signal. A data comparator is coupled to the data terminal and the sense amplifier and configured to compare the new data signal to the old data signal and to generate a comparator signal. A voltage generator is configured to selectively apply one of a read set of voltages to read a selected cell in the flash transistor array, a program set of voltages to program a selected cell and an erase set of voltages to erase a selected cell. In a multistate embodiment, the read/write controller further includes a step counter configured to generate a plurality of step counts. The voltage generator is coupled to the step counter and configured to generate a wordline high voltage (WLHV) signal based on the step count. The WLHV signal is delivered to a selected multistate cell by the wordline decoder to read the contents of the selected multistate cell. Each step compares the old data and the new data in order to determine which memory cells to change. Advantages of the invention include increased flexibility of programming and erasing and improved memory longevity.
摘要翻译：闪速存储器包括闪存晶体管阵列，字线解码器，位线解码器，源线解码器和读/写控制器。读/写控制器具有用于接收输入电压的电压端子和用于接收新数据信号的数据端子。感测放大器耦合到位线解码器并且被配置为感测所选位线上的信号并产生内部旧数据信号。数据比较器耦合到数据终端和读出放大器，并被配置为将新数据信号与旧数据信号进行比较并产生比较器信号。电压发生器被配置为选择性地施加读取的一组电压以读取闪存晶体管阵列中的所选择的单元，编程所选择的单元的电压的编程组和擦除所选择的单元的擦除组。在多状态实施例中，读/写控制器还包括配置成产生多个步数的步数计数器。电压发生器耦合到台阶计数器并且被配置为基于步数产生字线高电压（WLHV）信号。 WLHV信号由字线解码器传送到选定的多状态单元，以读取所选择的多状态单元的内容。每个步骤都比较旧数据和新数据，以确定要更改的存储单元。本发明的优点包括增加编程和擦除的灵活性并改善记忆寿命。

26. 发明授权

US5774396A Flash memory with row redundancy 失效
标题翻译：具有行冗余的闪存
公开(公告)号：US5774396A
公开(公告)日：1998-06-30
申请号：US762707
申请日：1996-12-09
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C8/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/06
CPC分类号： G11C16/3413 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C8/08 , G11C8/10 , H01L27/115 , G11C16/24 , G11C2211/5642 , G11C2211/5644 , G11C2216/20 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： The invention provides a flash memory with row redundancy. The memory includes an input terminal to receive an address and a command signal. A plurality of flash memory arrays are arranged as blocks, where each block includes a plurality of transistors organized in rows and columns and having respective wordlines, bitlines and a sourceline. A wordline decoder is coupled to the input terminal and a portion of the plurality of blocks and configured to decode a portion of the address and to receive a control signal to selectively apply a predetermined voltage to a wordline. A bitline decoder is coupled to the input terminal and to the plurality of blocks and configured to decode a portion of the address and to selectively pass a predetermined bitline to an output terminal. A match circuit is coupled to the input terminal and to a portion of the plurality of blocks and configured to decode a portion of the address and to receive the control signal to selectively apply a predetermined voltage to a wordline. A control circuit is coupled to the wordline decoder and the match circuit and configured to selectively activate one of the wordline decoder and the match circuit by the control signal. Advantages of the invention include improved row redundancy for wordline replacement and block replacement.
摘要翻译：本发明提供具有行冗余性的闪速存储器。存储器包括用于接收地址和命令信号的输入端。多个闪速存储器阵列被布置为块，其中每个块包括以行和列组织的多个晶体管，并且具有相应的字线，位线和源极线。字线解码器耦合到输入端和多个块的一部分，并且被配置为对地址的一部分进行解码，并且接收控制信号以选择性地将预定电压施加到字线。位线解码器耦合到输入端和多个块并且被配置为对地址的一部分进行解码，并选择性地将预定位线传递到输出端。匹配电路耦合到输入端和多个块的一部分，并且被配置为对地址的一部分进行解码并接收控制信号以选择性地将预定电压施加到字线。控制电路耦合到字线解码器和匹配电路，并且被配置为通过控制信号选择性地激活字线解码器和匹配电路中的一个。本发明的优点包括改进用于字线替换和块替换的行冗余。

27. 发明授权

US5748545A Memory device with on-chip manufacturing and memory cell defect detection capability 失效
标题翻译：具有片上制造和存储单元缺陷检测能力的存储器件
公开(公告)号：US5748545A
公开(公告)日：1998-05-05
申请号：US834775
申请日：1997-04-03
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C29/02 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/02 , G06F2201/81
摘要： A memory device with an on-chip manufacturing and memory cell defect detection capability includes a memory array with a plurality of memory cells that are organized in rows and columns, a plurality of word lines that interconnect respectively the rows of memory cells, and a plurality of bit lines that interconnect respectively the columns of memory cells. Global word line short and global word line open testing circuits are provided to detect the presence of a word line short or word line open condition. Local word line short and local word line open testing circuits are provided to identify the defective word line. Global bit line short and global bit line open testing circuits are provided to detect the presence of a bit line short or bit line open condition. A local bit line short/open testing circuit is used to identify the defective bit line. Short circuiting between word lines and bit lines, and the maximum and minimum threshold voltages of the memory cells can also be detected in the disclosed memory device.
摘要翻译：具有片上制造和存储单元缺陷检测能力的存储器件包括：存储器阵列，其具有以行和列组织的多个存储器单元;分别互连存储器单元的行的多条字线;以及多个的位线，分别互连存储器单元的列。提供全局字线短和全局字线打开测试电路，以检测字线短或字线打开状态的存在。提供本地字线短路和本地字线打开测试电路以识别有缺陷的字线。提供全局位线短路和全局位线开路测试电路，以检测位线短路或位线开路状况的存在。本地位线短路/开路测试电路用于识别有缺陷的位线。在所公开的存储器件中也可以检测字线和位线之间的短路以及存储单元的最大和最小阈值电压。

28. 发明授权

US5748538A OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array 失效
标题翻译：用于具有基于位的写入能力的闪存的OR平面存储单元阵列，以及用于编程和擦除存储单元阵列的方法
公开(公告)号：US5748538A
公开(公告)日：1998-05-05
申请号：US746665
申请日：1996-11-14
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C8/10 , G11C8/12 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/00
CPC分类号： G11C16/3413 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3445 , G11C16/3459 , G11C8/08 , G11C8/10 , G11C8/12 , H01L27/115 , G11C16/24 , G11C2211/5644 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： A memory cell array of a flash electrically erasable programmable read only memory (EEPROM) includes a plurality of transistor cells arranged in rows and columns. The sources of transistor cells in the same memory block are connected to a main source line through a control gate, as are the drains. The separate source and drains in the column direction are designed for a bit-based write capability. Writing, such as erasing or programming, of a selected transistor cell uses the Fowler-Nordheim tunneling method and can be accomplished due to the programming or erase inhibit voltage that is applied to non-selected transistor cells. The associated circuitry for bit-based writing, as well as methods of programming and erasing the memory cell array, with over-program and over-erase repair capability, are also disclosed.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）的存储单元阵列包括以行和列排列的多个晶体管单元。同一存储器块中的晶体管单元的源极通过控制栅极连接到主源极线，漏极也如此。列方向上的独立源和漏极被设计用于基于位的写入能力。所选择的晶体管单元的写入，例如擦除或编程使用Fowler-Nordheim隧道方法，并且可以由于施加到未选择的晶体管单元的编程或擦除禁止电压而实现。还公开了用于基于位的写入的相关电路，以及编程和擦除存储器单元阵列的方法，具有过程编程和过擦除修复能力。

29. 发明授权

US5646890A Flexible byte-erase flash memory and decoder 失效
标题翻译：灵活的字节擦除闪存和解码器
公开(公告)号：US5646890A
公开(公告)日：1997-07-08
申请号：US624322
申请日：1996-03-29
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/10 , G11C11/56 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/34 , G11C16/00
CPC分类号： G11C16/3427 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3418 , G11C8/10 , G11C2211/5642 , G11C2216/20 , G11C8/00
摘要： A flexible word-erase flash memory includes a first bank of flash transistors forming a plurality of rows and a plurality of columns, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the first bank are all coupled to a first sourceline. A second bank of flash transistors form a plurality of rows and a plurality of columns, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the second bank are all coupled to a second sourceline. A wordline decoder is coupled to the wordlines and configured to receive a wordline address signal and to decode the wordline address signal to select a wordline. A bitline decoder is coupled to the bitlines and configured to receive a bitline address signal and to decode the bitline address signal to select a predetermined plurality of bitlines. A sourceline latch is coupled to the first sourceline and the second sourceline and configured to latch a selected sourceline to selectively provide a sourceline erase voltage on the selected sourceline. Advantages of the invention include reduced stress on transistors not selected to be erased. This reduces program time by selectively erasing only those transistors needing reprogramming and promotes longevity of the flash memory transistors by erasing only the selected transistors.
摘要翻译：灵活的字擦除闪速存储器包括形成多行和多列的第一组闪存晶体管，其中每行中的晶体管的栅极耦合到公共字线，每列中的晶体管的漏极耦合到公共位线和第一组中的晶体管的源极都耦合到第一源极线。闪存晶体管的第二组形成多个行和多个列，其中每行中的晶体管的栅极耦合到公共字线，每列中的晶体管的漏极耦合到公共位线和晶体管的源极第二个银行都连接到第二个来源线。字线解码器耦合到字线并且被配置为接收字线地址信号并解码字线地址信号以选择字线。位线解码器耦合到位线并且被配置为接收位线地址信号并且解码位线地址信号以选择预定的多个位线。源极线锁存器耦合到第一源极线路和第二源极线路，并被配置为锁存所选择的源极线以选择性地在所选择的源极线路上提供源极线路擦除电压。本发明的优点包括未选择被擦除的晶体管上的应力降低。这通过仅选择性地擦除需要重新编程的晶体管并通过仅擦除所选择的晶体管来促进闪存晶体管的寿命来减少编程时间。

30. 发明授权

US5682350A Flash memory with divided bitline 失效
标题翻译：闪存分频线
公开(公告)号：US5682350A
公开(公告)日：1997-10-28
申请号：US726670
申请日：1996-10-07
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C8/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/00
CPC分类号： G11C16/3409 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , G11C16/3404 , G11C16/3413 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C8/08 , G11C8/10 , H01L27/115 , G11C16/24 , G11C2211/5642 , G11C2211/5644 , G11C2216/20 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： A flash memory includes a bank of flash transistors forming a plurality of rows and a plurality of columns, each flash transistor having a gate, drain and source, where the gates of flash transistors in each row are coupled to common wordlines, the drains of flash transistors in each column are coupled to common metal 1 lines divided into even metal 1 lines and odd metal 1 lines and the sources of the flash transistors are coupled to a common sourceline. A set of first selection transistors are coupled between even metal 1 lines and metal 2 lines having a pitch twice that of said metal 1 lines and controlled by a first select signal to selectively couple the even metal 1 lines to the metal 2 lines. A set of second selection transistors are coupled between odd metal 1 lines and the metal 2 lines and controlled by a second select signal to selectively couple the odd metal 1 lines to the metal 2 lines. In one embodiment, the set of first selection transistors and the set of second selection transistors are large in comparison to the flash transistors. Advantages of the invention include improved selection of memory cells, higher memory cell density and lower resistance in the memory cell selection circuitry.
摘要翻译：闪速存储器包括形成多行和多列的闪存晶体管组，每个闪存晶体管具有栅极，漏极和源极，其中每行中的闪存晶体管的栅极耦合到公共字线，闪存的漏极每列中的晶体管耦合到分为偶数金属1线和奇数金属1线的公共金属1线，并且闪存晶体管的源耦合到公共源极线。一组第一选择晶体管耦合在偶数金属1线和金属2线之间，金属2线具有两倍于所述金属1线的间距，并由第一选择信号控制，以选择性地将偶数金属1线耦合到金属2线。一组第二选择晶体管耦合在奇数金属1线和金属2线之间，并由第二选择信号控制，以将奇数金属1线选择性地耦合到金属2线。在一个实施例中，与闪存晶体管相比，该组第一选择晶体管和该组第二选择晶体管较大。本发明的优点包括存储器单元的改进选择，更高的存储单元密度和较低的存储单元选择电路中的电阻。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式