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11. 发明公开

EP0156648A2 Convolution arithmetic circuit for digital signal processing 失效
标题翻译： Arthmetische Konvolutionsschaltungfürdigitale Signalverarbeitung。
公开(公告)号：EP0156648A2
公开(公告)日：1985-10-02
申请号：EP85302161.6
申请日：1985-03-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Konishi, Kazuo c/o Patent Division , Nishikawa, Meisei c/o Patent Division
IPC分类号： G06F15/336 , H03H17/06 , G06F7/544 , H03H17/02
CPC分类号： H03H17/0238 , G06F7/5443
摘要： A convolution arithmetic circuit has a multiplier/accumulator to multiply two digital data sequences and add up the products. The sequences are stored in memories which cycle at the same rates and with different scales. One memory containing the multiplicand data is periodically updated, while the other memory containing coefficient data has a storage capacity of about twice the previous memory.
摘要翻译：卷积运算电路具有乘法器/累加器来乘以两个数字数据序列并将乘积相加。序列存储在以相同速率和不同尺度循环的存储器中。包含被乘数数据的一个存储器被周期性地更新，而包含系数数据的其它存储器的存储容量是前一存储器的大约两倍。

12. 发明申请

US20180226953A1 FIR FILTER CIRCUIT DESIGN METHOD USING APPROXIMATE COMPUTING 审中-公开
公开(公告)号：US20180226953A1
公开(公告)日：2018-08-09
申请号：US15883104
申请日：2018-01-30
申请人： UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
发明人： Seokhyeong KANG , Yesung KANG
IPC分类号： H03H17/02
CPC分类号： H03H17/0238 , H03H17/0223 , H03H17/06 , H03H2017/0081 , H03H2017/0245
摘要： A finite impulse response (FIR) filter circuit design method using approximate computing, the FIR filter circuit design method including: replacing adders of the FIR filter with approximate adders; and performing a synthesis work according to a set approximate synthesis flow when the replacing of the adders of the FIR filter are replaced with the approximate adders is performed, wherein, in the approximate synthesis flow, a numeric column of each of the approximate adders is divided into an accurate part and an inaccurate part, and a numeric column of the inaccurate part is approximated. In the FIR filter, conventional adders/subtractors are replaced with addition/subtraction having an automated synthesis flow so that energy consumption can be reduced.

13. 发明授权

US06711598B1 Method and system for design and implementation of fixed-point filters for control and signal processing 失效
标题翻译：用于控制和信号处理的定点滤波器的设计和实现方法和系统
公开(公告)号：US06711598B1
公开(公告)日：2004-03-23
申请号：US09710410
申请日：2000-11-10
申请人： Thomas E. Paré, Jr. , Daniel Joseph Hernandez , Cecilia Gabriela Galarza , Mark Alan Erickson , Sunil C. Shah
发明人： Thomas E. Paré, Jr. , Daniel Joseph Hernandez , Cecilia Gabriela Galarza , Mark Alan Erickson , Sunil C. Shah
IPC分类号： G06F1710
CPC分类号： H04L25/0204 , H03H17/0238 , H04B3/32 , H04M3/2209 , H04M3/244 , H04M3/303
摘要： A method and system is disclosed for design and implementation of fixed-point filters from floating-point filters. A design sequence for designing a fixed-point filter for a system is selected. A low-order floating-point filter and a first set of parameters associated with the low-order floating-point filter components are then selected. One or more parameters of the first set of parameters is then iteratively modified to obtain a set of modified parameters, until a plurality of performance characteristics calculated using the first set of parameters meets a performance objective for the fixed-point filter for the system.
摘要翻译：公开了一种用于从浮点滤波器设计和实现定点滤波器的方法和系统。选择用于设计系统的定点滤波器的设计顺序。然后选择低阶浮点滤波器和与低阶浮点滤波器分量相关联的第一组参数。然后迭代地修改第一组参数的一个或多个参数以获得一组修改的参数，直到使用第一组参数计算的多个性能特征满足系统的定点滤波器的性能目标。

14. 发明授权

US5886914A Filter circuit with reduced number of delay elements and adders 失效
标题翻译：具有减少数量的延迟元件和加法器的滤波电路
公开(公告)号：US5886914A
公开(公告)日：1999-03-23
申请号：US892968
申请日：1997-07-15
申请人： Satoshi Sugawa , Shiro Hosotani
发明人： Satoshi Sugawa , Shiro Hosotani
IPC分类号： G06F17/15 , H03H17/02 , G06F17/10
CPC分类号： H03H17/0238 , G06F17/15
摘要： An output from an adder 10.sub.1, i.e., an output of a first bit plane is inputted to an adder 10.sub.6 through delay elements 2.sub.2 and 3.sub.0 and a multiplier 100.sub.0. On the other hand, input data X are inputted to multipliers C.sub.2.sup.1 to C.sub.0.sup.1 through a delay element 1.sub.0 and multiplied by the respective multipliers to obtain partial products. An adder 10.sub.2 receives a partial product by the multiplier C.sub.2.sup.1 through a delay element 2.sub.3 and a partial product by the multiplier C.sub.1.sup.1. An adder 10.sub.3 receives an output from the adder 10.sub.2 through the delay element 2.sub.3 and on the other hand a partial product by the multiplier C.sub.0.sup.1. An output from the adder 10.sub.3, i.e., an output of a second bit plane is inputted to the adder 10.sub.6 through a delay element 2.sub.5. The adder 10.sub.6 performs addition of the output from the adder 10.sub.3, i.e., the output of the second bit plane and the output from the adder 10.sub.1, i.e., the output of the first bit plane, to output the addition result. This structure allows reduction in the number of delay elements and adders, to achieve a filter circuit downsized in circuit scale.
摘要翻译：来自加法器101的输出即第一位平面的输出通过延迟元件22和30以及乘法器1000输入到加法器106.另一方面，输入数据X通过一个输入数据X输入到乘法器C21至C01 延迟元件10并乘以相应的乘法器以获得部分乘积。加法器102通过延迟元件23由乘法器C21接收部分积，乘法器C11接收部分乘积。加法器103通过延迟元件23接收来自加法器102的输出，另一方面由乘法器C01接收部分乘积。来自加法器103的输出即第二位平面的输出通过延迟元件25输入到加法器106.加法器106执行加法器103的输出，即第二位平面的输出和加法器101的输出，即第一位平面的输出，以输出相加结果。这种结构允许减少延迟元件和加法器的数量，以实现电路规模缩小的滤波器电路。

15. 发明申请

WO2012018093A1 信号処理装置、テレビ、信号処理方法、プログラムおよび記録媒体审中-公开
标题翻译：信号处理装置，电视，信号处理方法，程序和记录介质
公开(公告)号：WO2012018093A1
公开(公告)日：2012-02-09
申请号：PCT/JP2011/067897
申请日：2011-08-04
申请人：シャープ株式会社 , 村橋善光
发明人：村橋　善光
IPC分类号： H03H17/02 , H04R3/04
CPC分类号： H03H17/0461 , H03H17/0238 , H03H17/0263 , H03H17/0286 , H03H2017/0295 , H03H2017/0298 , H03H2017/0477 , H04R3/00 , H04R2499/15
摘要：　音声処理部（１１２）は、独立した特性を有するｎ個の双二次フィルタを音声信号に順に作用させるイコライザ部（１１２１）とｎ個のフィルタで構成し得る順列についてｎ個のフィルタをその順で作用させてイコライザ部からの出力ノイズの大きさを推定する推定部（１１２４）と推定された大きさに基づき、出力ノイズが減るよう各フィルタの係数を入れ替えてｎ個のフィルタの作用順を実質的に変更する設定部（１１２３）とを備える。
摘要翻译：声音处理单元（112）具有：均衡器部分（1121），其使得具有各个特性的n个二次滤波器在声音信号上顺序地起作用; 估计部分（1124），其通过使n个滤波器依次作用于可以配置有n个滤波器的排列来估计来自均衡器部分的输出噪声的幅度; 以及通过基于所估计的幅度替换滤波器的系数使得输出的噪声减小而大大改变n个滤波器的动作序列的设定部分（1123）。

16. 发明申请

WO0241490A3 DIGITAL FILTER WITH STATE STORAGE 审中-公开
标题翻译：数据过滤器与状态存储
公开(公告)号：WO0241490A3
公开(公告)日：2003-01-23
申请号：PCT/US0147366
申请日：2001-11-03
申请人： QUALCOMM INC
发明人： MOHSENI JAFAR M , BUTLER BRIAN K , JOHN DEEPU , ZHANG HAITAO
IPC分类号： G06F17/10 , H03H17/02 , H03H17/06 , H04L25/03
CPC分类号： H03H17/0657 , H03H17/0226 , H03H17/0238 , H03H17/06 , H03H17/0607
摘要： A system for digital filtering includes a set of logic gates, a state storage, and a multiplexer. The state storage includes two or more storage banks and may also include combinatorial logic and/or at least one lookup table. In one application, a filtering operation according to a finite-impulse-response filter coefficient vector is performed without runtime multiplications. Applications to symmetric and antisymmetric filter coefficient vectors are described, as well as applications to filter coefficient vectors of arbitrary odd or even length.
摘要翻译：用于数字滤波的系统包括一组逻辑门，状态存储器和多路复用器。状态存储器包括两个或多个存储体，并且还可以包括组合逻辑和/或至少一个查找表。在一个应用中，执行根据有限脉冲响应滤波器系数向量的滤波操作，而不进行运行时乘法。对对称和反对称滤波器系数向量的应用进行了描述，以及用于滤除任意奇数或偶数长度的系数向量的应用。

17. 发明申请

WO99007071A1 ADAPTIVE FILTER SYSTEM HAVING MIXED FIXED POINT OR FLOATING POINT AND BLOCK SCALE FLOATING POINT OPERATORS 审中-公开
标题翻译：具有混合固定点或浮点的自适应滤波系统和块尺度浮点运算符
公开(公告)号：WO99007071A1
公开(公告)日：1999-02-11
申请号：PCT/US1998/013838
申请日：1998-07-02
IPC分类号： H03H17/02 , H03H17/06 , H03H21/00 , H04B3/23
CPC分类号： H03H17/0238 , H03H17/0227 , H03H21/0012
摘要： An adaptive filter is provided which has fixed point or floating point data stored in a data RAM (74) and block scale floating point coefficients stored in a coefficient RAM (84). The data and coefficients are utilized in a filter algorithm which utilizes a multiplier and an accumulator to provide a convolution result. Coefficients are uptdated by adding the multiplied result of the data RAM value and the error value to the old value of the coefficient. This is done for all the coefficient values in the coefficient RAM. The error value indicates the difference between the filter output and the sample near-end signal that is the echo. These new coefficients are examined and if any have a value above or all have a value below a predetermined threshold, then the mantissas of all the coefficents are shifted and the exponent adjusted in the next filter cycle.
摘要翻译：提供了一种自适应滤波器，其具有存储在数据RAM（74）中的固定点或浮点数据以及存储在系数RAM（84）中的块比例浮点系数。数据和系数被用在利用乘法器和累加器来提供卷积结果的滤波器算法中。通过将数据RAM值的相乘结果和误差值相加到系数的旧值来升高系数。这是对系数RAM中的所有系数值进行的。误差值表示滤波器输出与作为回波的样本近端信号之间的差异。检查这些新系数，并且如果有的值高于或全部具有低于预定阈值的值，则所有系数的尾数被移动，并且在下一个滤波周期中调整指数。

18. 发明公开

EP1332552A2 DIGITAL FILTER WITH STATE STORAGE 有权
标题翻译：与固态存储数字滤波器
公开(公告)号：EP1332552A2
公开(公告)日：2003-08-06
申请号：EP01992057.8
申请日：2001-11-03
申请人： QUALCOMM INCORPORATED
发明人： MOHSENI, Jafar, M. , BUTLER, Brian, K. , JOHN, Deepu , ZHANG, Haitao
IPC分类号： H03H1/00
CPC分类号： H03H17/0657 , H03H17/0226 , H03H17/0238 , H03H17/06 , H03H17/0607
摘要： A system for digital filtering includes a set of logic gates, a state storage, and a multiplexer. The state storage includes two or more storage banks and may also include combinatorial logic and/or at least one lookup table. In one application, a filtering operation according to a finite-impulse-response filter coefficient vector is performed without runtime multiplications. Applications to symmetric and antisymmetric filter coefficient vectors are described, as well as applications to filter coefficient vectors of arbitrary odd or even length.

19. 发明授权

EP0156648B1 Convolution arithmetic circuit for digital signal processing 失效
标题翻译：数字信号处理的调制算法电路
公开(公告)号：EP0156648B1
公开(公告)日：1992-09-30
申请号：EP85302161.6
申请日：1985-03-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Konishi, Kazuo c/o Patent Division , Nishikawa, Meisei c/o Patent Division
IPC分类号： G06F15/336 , H03H17/06 , G06F7/544 , H03H17/02
CPC分类号： H03H17/0238 , G06F7/5443

20. 发明专利

JP2012039232A Signal processor, television, signal processing method, program and recording medium 审中-公开
标题翻译：信号处理器，电视，信号处理方法，程序和记录介质
公开(公告)号：JP2012039232A
公开(公告)日：2012-02-23
申请号：JP2010175389
申请日：2010-08-04
申请人： Sharp Corp , シャープ株式会社
发明人： MURAHASHI YOSHIMITSU
IPC分类号： H03H17/02 , G10L21/02 , G10L21/04 , H04R3/04
CPC分类号： H03H17/0461 , H03H17/0238 , H03H17/0263 , H03H17/0286 , H03H2017/0295 , H03H2017/0298 , H03H2017/0477 , H04R3/00 , H04R2499/15
摘要： PROBLEM TO BE SOLVED: To provide a signal processor for making the amount of noise generated in signal processing smaller than before even when it is provided as a signal processor including an inexpensive fixed point operation DSP.SOLUTION: A sound processing section 112 includes: an equalizer section 1121 for making n pieces of biquadratic filters 1121-1 to 1121-n having independent filter characteristics successively act on sound signals; a noise level estimation section 1124 for estimating the size of noise to be outputted from the equalizer section 1121 by making the n pieces of biquadratic filters act in the order to the sound signals for permutation which can be constituted of the n pieces of biquadratic filters; and a filter coefficient setting section 1123 for practically changing the order of making the n pieces of biquadratic filters act on input signals by changing the filter coefficients of the respective biquadratic filters so as to reduce the noise outputted from the equalizer section 1121 on the basis of the estimated size of the noise.
摘要翻译：要解决的问题：提供一种信号处理器，用于使信号处理中产生的噪声量比以前更小，即使当其被提供为包括便宜的定点运算DSP的信号处理器时。解决方案：声音处理部分112包括：均衡器部分1121，用于使n个具有独立滤波器特性的双二次滤波器1121-1至1121-n依次作用在声音信号上; 噪声电平估计部分1124，用于通过使得n个双二次滤波器按照可以由n个双二次滤波器构成的置换声音信号的顺序来估计从均衡器部分1121输出的噪声的大小; 以及滤波器系数设定部分1123，用于通过改变各个二次滤波器的滤波器系数来实际改变使n个双二进制滤波器的顺序对输入信号起作用，以便基于均衡器部分1121输出的噪声估计的噪音大小。版权所有（C）2012，JPO＆INPIT

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