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11. 发明授权

US09646953B2 Integrated circuit packaging techniques and configurations for small form-factor or wearable devices 有权
公开(公告)号：US09646953B2
公开(公告)日：2017-05-09
申请号：US14775550
申请日：2014-11-12
申请人： INTEL CORPORATION
发明人： Jackson Chung Peng Kong , Bok Eng Cheah , Kooi Chi Ooi , Shanggar Periaman , Michael P. Skinner
IPC分类号： H01L25/065 , H01L23/31 , H01L23/367 , H01L21/48 , A44B1/00 , G06F1/16 , H01L25/00 , H01L23/48 , A45C1/06 , B43K29/00 , G02C11/00 , H01L21/56 , H01L23/498 , H01L23/00
CPC分类号： H01L25/0655 , A44B1/00 , A45C1/06 , B43K29/00 , G02C11/10 , G06F1/163 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/4882 , H01L21/565 , H01L21/568 , H01L23/13 , H01L23/147 , H01L23/3114 , H01L23/3121 , H01L23/36 , H01L23/3675 , H01L23/48 , H01L23/481 , H01L23/49805 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/5384 , H01L23/552 , H01L24/19 , H01L24/20 , H01L24/96 , H01L25/0652 , H01L25/50 , H01L2224/02371 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/16235 , H01L2224/24137 , H01L2224/32245 , H01L2224/73267 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06551 , H01L2225/06572 , H01L2225/06589 , H01L2924/10155 , H01L2924/1016 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/15158 , H01L2924/15192 , H01L2924/157 , H01L2924/15788 , H01L2924/18161
摘要： Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable devices. In one embodiment, an apparatus may include a substrate having a first side and a second side disposed opposite to the first side and a sidewall disposed between the first side and the second side, the sidewall defining a perimeter of the substrate, and a plurality of through-substrate vias (TSVs) disposed between the first side and the second side of the substrate, and a first dielectric layer disposed on the first side and including electrical routing features to route electrical signals of one or more dies in a plane of the first dielectric layer. Other embodiments may be described and/or claimed.

12. 发明申请

US20170033070A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20170033070A1
公开(公告)日：2017-02-02
申请号：US15168550
申请日：2016-05-31
申请人： Renesas Electronics Corporation
发明人： Takafumi BETSUI , Motoo SUWA
IPC分类号： H01L23/00 , H01L25/065 , H01L23/498
CPC分类号： H01L24/17 , H01L23/498 , H01L23/49838 , H01L23/50 , H01L25/0655 , H01L2224/16227 , H01L2924/1016 , H01L2924/1431 , H01L2924/1432 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105
摘要： Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed. In a region of the wiring substrate where the second circuit is close to the first circuit, a voltage line which supplies the power supply voltage to the second circuit is formed.
摘要翻译：可以防止尺寸增大的半导体装置。半导体器件包括具有第一主表面和与第一主表面相对的第二主表面的半导体芯片和布线基板，半导体芯片的第二主表面安装在该基板上，使得半导体芯片的第二主表面面向第一主表面布线基板。在半导体芯片的第二主表面上，布置有与第一电路连接的多个第一端子和与第二电路连接的多个第二端子。多个第一端子的布置图案和多个第二端子的布置图案包括相同的布置图案。在从半导体芯片的第一主表面观察第一电路接近第二电路的布线基板的区域中形成向第一电路提供电源电压的电压线。在第二电路接近第一电路的布线基板的区域中，形成向第二电路供给电源电压的电压线。

13. 发明授权

US06812549B2 Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument 有权
标题翻译：接线板及其制造方法，半导体器件及其制造方法，电路板和电子仪器
公开(公告)号：US06812549B2
公开(公告)日：2004-11-02
申请号：US10273885
申请日：2002-10-21
申请人： Kazushige Umetsu , Yohei Kurashima , Jun Amako
发明人： Kazushige Umetsu , Yohei Kurashima , Jun Amako
IPC分类号： H01L2940
CPC分类号： H01L21/486 , H01L21/76882 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/0401 , H01L2224/051 , H01L2224/05563 , H01L2224/05567 , H01L2224/0557 , H01L2224/05572 , H01L2224/056 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/1181 , H01L2224/11849 , H01L2224/13009 , H01L2224/1319 , H01L2224/13411 , H01L2224/13444 , H01L2224/13483 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/17181 , H01L2224/811 , H01L2224/81191 , H01L2224/81193 , H01L2224/814 , H01L2224/8149 , H01L2224/81815 , H01L2224/8185 , H01L2224/9202 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/1016 , H01L2924/1017 , H01L2924/12042 , H01L2924/14 , H05K3/3494 , H05K3/4038 , H05K2201/0305 , H05K2201/096 , H05K2203/041 , H05K2203/082 , H05K2203/107 , H01L2924/0105 , H01L2224/05552 , H01L2924/00
摘要： A conductive material is provided to an open end of a penetrating hole penetrating through at least a semiconductor element, on the side of a first surface of the semiconductor element. The conductive material is melted to flow into the penetrating hole. The conductive material is made to flow into the penetrating hole in a state that an atmospheric pressure on the side of a second surface of the semiconductor element opposite to the first surface is lower than an atmospheric pressure on the side of the first surface.
摘要翻译：在半导体元件的第一表面侧的贯通至少半导体元件的穿透孔的开口端设有导电材料。导电材料熔化以流入穿透孔。使导电材料以与第一表面相反的半导体元件的第二表面侧的大气压低于第一表面侧的大气压的状态流入贯通孔。

14. 发明申请

WO2016076865A1 INTEGRATED CIRCUIT PACKAGING TECHNIQUES AND CONFIGURATIONS FOR SMALL FORM-FACTOR OR WEARABLE DEVICES 审中-公开
标题翻译：集成电路封装技术和配置小型或易损设备
公开(公告)号：WO2016076865A1
公开(公告)日：2016-05-19
申请号：PCT/US2014/065313
申请日：2014-11-12
申请人： INTEL CORPORATION
发明人： KONG, Jackson, Chung, Peng , CHEAH, Bok, Eng , OOI, Kooi, Chi , PERIAMAN, Shanggar , SKINNER, Michael, P.
IPC分类号： H01L23/48
CPC分类号： H01L25/0655 , A44B1/00 , A45C1/06 , B43K29/00 , G02C11/10 , G06F1/163 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/4882 , H01L21/565 , H01L21/568 , H01L23/13 , H01L23/147 , H01L23/3114 , H01L23/3121 , H01L23/36 , H01L23/3675 , H01L23/48 , H01L23/481 , H01L23/49805 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/5384 , H01L23/552 , H01L24/19 , H01L24/20 , H01L24/96 , H01L25/0652 , H01L25/50 , H01L2224/02371 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/16235 , H01L2224/24137 , H01L2224/32245 , H01L2224/73267 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06551 , H01L2225/06572 , H01L2225/06589 , H01L2924/10155 , H01L2924/1016 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/15158 , H01L2924/15192 , H01L2924/157 , H01L2924/15788 , H01L2924/18161
摘要： Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable devices. In one embodiment, an apparatus may include a substrate having a first side and a second side disposed opposite to the first side and a sidewall disposed between the first side and the second side, the sidewall defining a perimeter of the substrate, and a plurality of through-substrate vias (TSVs) disposed between the first side and the second side of the substrate, and a first dielectric layer disposed on the first side and including electrical routing features to route electrical signals of one or more dies in a plane of the first dielectric layer. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例涉及用于小尺寸或可佩戴装置的集成电路（IC）封装技术和配置。在一个实施例中，装置可以包括具有第一侧和与第一侧相对设置的第二侧和设置在第一侧和第二侧之间的侧壁的衬底，侧壁限定衬底的周边，以及多个布置在基板的第一侧和第二侧之间的贯通基板通孔（TSV）以及布置在第一侧上的第一介电层，并且包括电路径特征以将一个或多个管芯的电信号路由在第一电介质层。可以描述和/或要求保护其他实施例。

16. 发明授权

US09831209B2 Semiconductor device 有权
公开(公告)号：US09831209B2
公开(公告)日：2017-11-28
申请号：US15168550
申请日：2016-05-31
申请人： Renesas Electronics Corporation
发明人： Takafumi Betsui , Motoo Suwa
IPC分类号： G06F17/50 , H01L23/00 , H01L23/498 , H01L25/065
CPC分类号： H01L24/17 , H01L23/498 , H01L23/49838 , H01L23/50 , H01L25/0655 , H01L2224/16227 , H01L2924/1016 , H01L2924/1431 , H01L2924/1432 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105
摘要： Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed. In a region of the wiring substrate where the second circuit is close to the first circuit, a voltage line which supplies the power supply voltage to the second circuit is formed.

17. 发明申请

US20160365295A1 SEMICONDUCTOR ARRANGEMENT, SEMICONDUCTOR SYSTEM AND METHOD OF FORMING A SEMICONDUCTOR ARRANGEMENT 审中-公开
标题翻译：半导体布置，半导体系统和形成半导体布置的方法
公开(公告)号：US20160365295A1
公开(公告)日：2016-12-15
申请号：US15149207
申请日：2016-05-09
申请人： Infineon Technologies AG
发明人： Juergen HOEGERL , Edward FUERGUT
IPC分类号： H01L23/31 , H01L23/04 , H01L23/10 , H01L21/56 , H01L23/492
CPC分类号： H01L23/31 , H01L21/561 , H01L21/566 , H01L21/568 , H01L23/04 , H01L23/10 , H01L23/142 , H01L23/295 , H01L23/3121 , H01L23/3142 , H01L23/492 , H01L23/4924 , H01L23/4928 , H01L23/49562 , H01L23/49877 , H01L23/5386 , H01L23/544 , H01L24/06 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/40 , H01L24/48 , H01L24/50 , H01L24/66 , H01L24/69 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/86 , H01L24/89 , H01L24/92 , H01L24/97 , H01L29/7393 , H01L29/868 , H01L2223/54486 , H01L2224/04026 , H01L2224/06181 , H01L2224/24137 , H01L2224/2732 , H01L2224/291 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/29311 , H01L2224/29318 , H01L2224/29339 , H01L2224/29347 , H01L2224/29499 , H01L2224/32245 , H01L2224/33181 , H01L2224/40137 , H01L2224/48137 , H01L2224/73201 , H01L2224/73213 , H01L2224/73215 , H01L2224/73217 , H01L2224/73219 , H01L2224/73251 , H01L2224/73263 , H01L2224/73265 , H01L2224/73267 , H01L2224/83101 , H01L2224/83191 , H01L2224/83192 , H01L2224/83193 , H01L2224/83801 , H01L2224/83815 , H01L2224/83825 , H01L2224/8384 , H01L2224/8385 , H01L2224/83851 , H01L2224/83855 , H01L2224/84801 , H01L2224/8484 , H01L2224/8485 , H01L2224/92142 , H01L2224/92144 , H01L2224/92147 , H01L2224/92148 , H01L2224/92242 , H01L2224/92244 , H01L2224/92248 , H01L2224/97 , H01L2924/00014 , H01L2924/10155 , H01L2924/1016 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/1032 , H01L2924/10329 , H01L2924/10331 , H01L2924/10332 , H01L2924/10335 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15162 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2924/0103 , H01L2924/014 , H01L2224/83 , H01L2224/84 , H01L2224/85 , H01L2224/32 , H01L2224/69 , H01L2224/89 , H01L2224/82 , H01L2224/86 , H01L2224/45099
摘要： A semiconductor arrangement is provided. The semiconductor arrangement may include an electrically conductive plate having a surface, a plurality of power semiconductor devices arranged on the surface of the electrically conductive plate, wherein a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices may be electrically coupled to the electrically conductive plate, a plurality of electrically conductive blocks, wherein each electrically conductive block may be electrically coupled with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and encapsulation material encapsulating the plurality of power semiconductor devices, wherein at least one edge region of the surface of the electrically conductive plate may be free from the encapsulation material.
摘要翻译：提供了半导体布置。半导体布置可以包括具有表面的导电板，布置在导电板的表面上的多个功率半导体器件，其中多个功率半导体器件中的每个功率半导体器件的第一受控端可以电耦合导电板，多个导电块，其中每个导电块可以与多个功率半导体器件中的每个功率半导体器件的相应的第二受控端电耦合; 以及封装所述多个功率半导体器件的封装材料，其中所述导电板的表面的至少一个边缘区域可以不含所述封装材料。

18. 发明申请

US20030060000A1 Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument 有权
公开(公告)号：US20030060000A1
公开(公告)日：2003-03-27
申请号：US10273885
申请日：2002-10-21
申请人： Seiko Epson Corporation
发明人： Kazushige Umetsu , Yohei Kurashima , Jun Amako
IPC分类号： H01L021/8238
CPC分类号： H01L21/486 , H01L21/76882 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/0401 , H01L2224/051 , H01L2224/05563 , H01L2224/05567 , H01L2224/0557 , H01L2224/05572 , H01L2224/056 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/1181 , H01L2224/11849 , H01L2224/13009 , H01L2224/1319 , H01L2224/13411 , H01L2224/13444 , H01L2224/13483 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/17181 , H01L2224/811 , H01L2224/81191 , H01L2224/81193 , H01L2224/814 , H01L2224/8149 , H01L2224/81815 , H01L2224/8185 , H01L2224/9202 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/1016 , H01L2924/1017 , H01L2924/12042 , H01L2924/14 , H05K3/3494 , H05K3/4038 , H05K2201/0305 , H05K2201/096 , H05K2203/041 , H05K2203/082 , H05K2203/107 , H01L2924/0105 , H01L2224/05552 , H01L2924/00
摘要： A conductive material is provided to an open end of a penetrating hole penetrating through at least a semiconductor element, on the side of a first surface of the semiconductor element. The conductive material is melted to flow into the penetrating hole. The conductive material is made to flow into the penetrating hole in a state that an atmospheric pressure on the side of a second surface of the semiconductor element opposite to the first surface is lower than an atmospheric pressure on the side of the first surface.

19. 发明申请

US20180090462A1 INTEGRATED CIRCUIT PACKAGE HAVING RECTANGULAR ASPECT RATIO 审中-公开
公开(公告)号：US20180090462A1
公开(公告)日：2018-03-29
申请号：US15280425
申请日：2016-09-29
申请人： Scot A. Kellar , Darren S. Crews
发明人： Scot A. Kellar , Darren S. Crews
IPC分类号： H01L23/00 , H01L23/31 , H01L21/56
CPC分类号： H01L24/14 , H01L21/56 , H01L23/3114 , H01L23/3128 , H01L23/50 , H01L23/562 , H01L24/11 , H01L2224/1413 , H01L2924/1016 , H01L2924/1815 , H01L2924/3511
摘要： An integrated circuit (IC) packaging arrangement for surface mounting of the IC includes a package body that encapsulates one or more IC dies. The package body according to some embodiments has rectangular aspect ratio with a length dimension and a width dimension of different size. The IC packaging according to some embodiments includes leadless surface-mount electrical contacts. According to some embodiments, the leadless surface-mount contacts are situated in clusters at opposite ends of the length dimension of the IC body.

20. 发明申请

US20180068971A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180068971A1
公开(公告)日：2018-03-08
申请号：US15795365
申请日：2017-10-27
申请人： Renesas Electronics Corporation
发明人： Takafumi BETSUI , Motoo SUWA
IPC分类号： H01L23/00 , H01L23/498 , H01L25/065
CPC分类号： H01L24/17 , H01L23/498 , H01L23/49838 , H01L23/50 , H01L25/0655 , H01L2224/16227 , H01L2924/1016 , H01L2924/1431 , H01L2924/1432 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105
摘要： Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed. In a region of the wiring substrate where the second circuit is close to the first circuit, a voltage line which supplies the power supply voltage to the second circuit is formed.

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