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11. 发明公开

CN103608822A 掩饰电子装置寿命终期转换的方法及包含相应控制模块的装置有权
公开(公告)号：CN103608822A
公开(公告)日：2014-02-26
申请号：CN201280014477.4
申请日：2012-01-10
申请人：茂福公司
发明人：马埃尔·伯西厄 , 迈克尔·巴塞
IPC分类号： G06F21/70
CPC分类号： G06F12/0246 , G06F21/55 , G06F21/558 , G06F21/75 , G06F21/755 , G06F2221/2143 , G09C1/00 , H04L9/004 , H04L63/1441
摘要：本发明涉及一种掩饰电子微处理器装置寿命终期转换的方法，包括含有寿命终期状态变量(FdVE)的可再编程非易失性存储器。变量值(FdVE)被下载(A)到随机存取存储器中。在执行任一当前命令(COM)之前，检查(B)随机存取存储器中的变量值(FdVR)。如果是空值，则执行(C)寿命终期转换。否则，继续(D)初始化或执行命令(COM)。如检测(E)到侵入攻击，寿命终期状态变量(FdVR)被写入(F)单随机存取存储器中，并从非易失性存储器中以延时的方式删除(G)寿命终期状态变量(FdVE)。本发明适合于所有电子装置，微处理器卡等等。

12. 发明公开

CN103309777A 电路装置、形成电路装置的方法和用于完整性检查的方法有权
公开(公告)号：CN103309777A
公开(公告)日：2013-09-18
申请号：CN201310056767.1
申请日：2013-02-22
申请人：英飞凌科技奥地利有限公司
发明人： W.富特纳
IPC分类号： G06F11/22
CPC分类号： G06F21/558 , G06F21/755 , G06F21/79 , Y10T29/49004
摘要：本发明涉及电路装置、形成电路装置的方法和用于完整性检查的方法。一种电路装置被提供，所述电路装置包括：处理器；存储电路，所述存储电路被连接到处理器，其中处理器被配置为访问存储电路；阻塞电路，所述阻塞电路被配置为生成阻止处理器访问存储电路的一个或多个随机等待状态信号；以及完整性检查电路，所述完整性检查电路被配置为在一个或多个随机等待状态信号的等待状态周期期间检查存储电路。

13. 发明授权

US09690928B2 Computing platform security methods and apparatus 有权
公开(公告)号：US09690928B2
公开(公告)日：2017-06-27
申请号：US14523886
申请日：2014-10-25
申请人： McAfee, Inc.
发明人： Paritosh Saxena , Adrian M. M. T. Dunbar , Michael S. Hughes , John Teddy , David Michael Durham , Balaji Vembu , Prashant Dewan , Debra Cablao , Nicholas D. Triantafillou , Jason M. Surprise
IPC分类号： G06F21/44 , G06F21/56 , G06F21/57 , G06F21/71 , G06F21/74
CPC分类号： G06F21/552 , G06F1/28 , G06F9/45558 , G06F9/5027 , G06F12/14 , G06F12/145 , G06F12/1491 , G06F21/445 , G06F21/554 , G06F21/558 , G06F21/56 , G06F21/566 , G06F21/57 , G06F21/71 , G06F21/74 , G06F2009/45587 , G06F2209/509 , G06F2212/1052 , G06F2221/034 , G06F2221/2149 , G06T1/20 , G09G5/363
摘要： Computing platform security methods and apparatus are disclosed. An example apparatus includes a security application to configure a security task, the security task to detect a malicious element on a computing platform, the computing platform including a central processing unit and a graphics processing unit; and an offloader to determine whether the central processing unit or the graphics processing unit is to execute the security task; and when the graphics processing unit is to execute the security task, offload the security task to the graphics processing unit for execution.

14. 发明授权

US09536086B2 Circuit arrangement, a method for forming a circuit arrangement, and method for integrity checking 有权
标题翻译：电路装置，形成电路装置的方法以及完整性检查方法
公开(公告)号：US09536086B2
公开(公告)日：2017-01-03
申请号：US13401885
申请日：2012-02-22
申请人： Wolfgang Furtner
发明人： Wolfgang Furtner
IPC分类号： G06F11/30 , G06F21/55 , G06F21/79
CPC分类号： G06F21/558 , G06F21/755 , G06F21/79 , Y10T29/49004
摘要： A circuit arrangement is provided, the circuit arrangement including a processor; a memory circuit connected to the processor, wherein the processor is configured to access the memory circuit; a blocking circuit configured to generate one or more random wait state signals which prevent the processor from accessing the memory circuit; and an integrity checking circuit configured to check the memory circuit during a wait state period of the one or more random wait state signals.
摘要翻译：提供一种电路装置，该电路装置包括处理器; 连接到所述处理器的存储器电路，其中所述处理器被配置为访问所述存储器电路; 阻塞电路，被配置为产生一个或多个随机等待状态信号，其阻止所述处理器访问所述存储器电路; 以及完整性检查电路，被配置为在所述一个或多个随机等待状态信号的等待状态期间检查所述存储器电路。

15. 发明授权

US09418225B2 Transmitting device and method of overlaying signals with the device 有权
标题翻译：传输设备和与设备重叠信号的方法
公开(公告)号：US09418225B2
公开(公告)日：2016-08-16
申请号：US14529640
申请日：2014-10-31
申请人： Fujitsu Technology Solutions Intellectual Property GmbH
发明人： Thorsten Höhnke
IPC分类号： H04L29/06 , G06F21/55 , H04B3/54
CPC分类号： G06F21/558 , G06F21/755 , G06F2221/2123 , H04B3/546 , H04B2203/5416 , H04B2203/5495
摘要： A transmitting device that transmits data signals into a primary electricity grid, wherein the transmitting device connects to a power input of a computer system and overlays signals returned by the computer system into the primary electricity grid by modulating random data signals onto a line connected to the power input of the computer system.
摘要翻译：一种将数据信号发送到一次电网中的发送装置，其中发送装置连接到计算机系统的电力输入端，并将计算机系统返回的信号叠加到主电网中，通过将随机数据信号调制到连接到计算机系统的电源输入。

16. 发明授权

US09141793B2 Method for securing a microprocessor, corresponding computer program and device 有权
标题翻译：用于固定微处理器，相应的计算机程序和设备的方法
公开(公告)号：US09141793B2
公开(公告)日：2015-09-22
申请号：US12344370
申请日：2008-12-26
申请人： David Naccache , Nora Dabbous
发明人： David Naccache , Nora Dabbous
IPC分类号： G06F12/14 , G06F21/55 , G06F21/75
CPC分类号： G06F21/558 , G06F21/75 , G06F21/755
摘要： A method is provided for securing a microprocessor containing at least one main program, which operates with at least one memory. The method includes implementing counter-measures, during which additional operations, that are not required for the main program, are implemented so as to modify the consumption of current and/or the processing time of the microprocessor. The method also includes: identification of at least one address or one memory zone of the memory(ies), called critical addresses, and which contain, or which may contain, critical data for said main program; monitoring the addressing ports of the memory(ies), so as to detect the access to the critical address(es); and activation of the step of implementing counter-measures, when an access to the critical address(es) is detected.
摘要翻译：提供了一种用于固定包含至少一个主程序的微处理器的方法，所述至少一个主程序与至少一个存储器一起操作。该方法包括实现对策，在此期间实施主程序不需要的附加操作，以便修改微处理器的当前和/或处理时间的消耗。该方法还包括：识别存储器的至少一个地址或一个存储器区域，称为关键地址，并且其包含或可以包含用于所述主程序的关键数据; 监视存储器的寻址端口，以便检测对关键地址的访问; 以及当检测到对关键地址的访问时，激活实施对策的步骤。

17. 发明申请

US20140053003A1 RANDOM TIMESLOT CONTROLLER FOR ENABLING BUILT-IN SELF TEST MODULE 有权
标题翻译：随机时间控制器，用于启动内置自检模块
公开(公告)号：US20140053003A1
公开(公告)日：2014-02-20
申请号：US13589580
申请日：2012-08-20
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F21/02 , G06F1/00
CPC分类号： G06F21/558 , G06F21/556 , G06F21/755
摘要： A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.
摘要翻译：一种具有第一处理器，第二处理器，第二处理器的本地存储器和第二处理器的内置自检（BIST）控制器的数据处理系统，其可以被随机地启用以对本地存储器执行存储器访问的第二处理器，并且包括随机值发生器。该系统可以执行包括由第一处理器执行安全代码序列并且由第二处理器的BIST控制器响应于随机值生成器对第二处理器的本地存储器进行BIST存储器访问的方法。执行BIST存储器访问同时执行安全代码序列。

18. 发明申请

US20110007567A1 TEMPORARY LOCKING OF AN ELECTRONIC CIRCUIT 有权
标题翻译：电子电路临时锁定
公开(公告)号：US20110007567A1
公开(公告)日：2011-01-13
申请号：US12521773
申请日：2008-01-04
申请人： Jean-Louis Modave , Thierry Huque
发明人： Jean-Louis Modave , Thierry Huque
IPC分类号： G11C16/22 , H03K19/00
CPC分类号： G07F7/084 , G04F10/10 , G06F21/558 , G06F21/75 , G06F21/755 , G06F21/77 , G06Q20/341 , G06Q20/3576 , G07F7/082 , G07F7/1008 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A method and a circuit for protecting at least one piece of information contained in an electronic circuit by disabling at least one function of the circuit in case of detection of a number of abnormal operations greater than a threshold, in which the disabling of the function is temporary, of a duration independent from whether the circuit is powered or not.
摘要翻译：一种用于通过在检测到大于阈值的多个异常操作的情况下禁用所述电路的至少一个功能来保护包含在电子电路中的至少一条信息的方法和电路，其中所述功能的禁用是暂时的，持续时间，不管电路是否通电。

19. 发明公开

EP3080746A4 GATE-LEVEL MASKING 有权
标题翻译： MASKIERUNG AUF GATE-EBENE
公开(公告)号：EP3080746A4
公开(公告)日：2017-09-06
申请号：EP14868741
申请日：2014-12-11
申请人： CRYPTOGRAPHY RES INC
发明人： LEISERSON ANDREW JOHN , MARSON MARK EVAN , WACHS MEGAN ANNEKE
IPC分类号： H04L9/00 , G06F21/55 , G06F21/71 , G06F21/72 , G06F21/76
CPC分类号： G06F21/72 , G06F21/558 , G06F21/71 , G06F21/755 , H04L9/003 , H04L2209/04 , H04L2209/12
摘要： A method of and system for gate-level masking of secret data during a cryptographic process is described. A mask share is determined, wherein a first portion of the mask share includes a first number of zero-values and a second number of one-values, and a second portion of the mask share includes the first number of one-values and the second number of zero-values. Masked data values and the first portion of the mask share are input into a first portion of masked gate logic, and the masked data values and the second portion of the mask share are input into a second portion of the masked gate logic. A first output from the first portion of the masked gate logic and a second output from the second portion of the masked gate logic are identified, wherein either the first output or the second output is a zero-value.
摘要翻译：描述了在密码处理期间秘密数据的门级掩蔽的方法和系统。确定掩码份额，其中掩码份额的第一部分包括第一数量的零值和第二数量的一值，并且掩码份额的第二部分包括第一数量的一值，第二数量的一值零值的数量。将掩模数据值和掩模份额的第一部分输入到掩蔽栅极逻辑的第一部分，并将掩蔽数据值和掩蔽份额的第二部分输入掩蔽栅极逻辑的第二部分。识别来自掩蔽栅极逻辑的第一部分的第一输出和来自掩蔽栅极逻辑的第二部分的第二输出，其中第一输出或第二输出是零值。

20. 发明公开

EP2746985A1 Cryptographic circuit protection from differential power analysis 有权
标题翻译： Kryptografischer Schaltungsschutz vor differentieller Leistungsanalyse
公开(公告)号：EP2746985A1
公开(公告)日：2014-06-25
申请号：EP13198109.4
申请日：2013-12-18
申请人： NXP B.V.
发明人： Nowottnick, Juergen
IPC分类号： G06F21/75 , G06F21/55
CPC分类号： G06F21/558 , G06F21/55 , G06F21/72 , G06F21/75 , G06F21/755 , G06F21/76 , G06F21/87
摘要： According to an example embodiment, a device provides cryptographic processing functions using secret data. The device can include protection from differential power analysis (DPA). The encryption processing circuit and its memory can be decoupled from external power source(s) during encryption-related computations. A local power storage element, such as a capacitive element, can provide power while the encryption processing circuit is decoupled from the external power source(s). The local power storage element can then be reconnected and charged once the encryption-related computations are completed or paused.
摘要翻译：根据示例实施例，设备使用秘密数据提供密码处理功能。该器件可以包括对差分功率分析（DPA）的保护。在加密相关计算期间，加密处理电路及其存储器可以与外部电源解耦。诸如电容元件的本地电力存储元件可以在加密处理电路与外部电源解耦时提供电力。一旦加密相关的计算完成或暂停，就可以重新连接和充电本地电力存储元件。

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