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11. 发明专利

JPH10116176A OBJECT REFERENCE MEMORY MAPPING 失效
公开(公告)号：JPH10116176A
公开(公告)日：1998-05-06
申请号：JP16723197
申请日：1997-06-24
申请人： CIRRUS LOGIC INC
发明人： LARSON MICHAEL KERRY
IPC分类号： G06F3/153 , G06T11/20 , G06T15/80
摘要： PROBLEM TO BE SOLVED: To reduce the total frequency of access to a memory and its necessary time and then make the system fast by increasing the number of pixels which are plotted by single access. SOLUTION: A polygon plotting command refers to specific information regarding a polygon to be plotted (301) and determines XY high-speed memory segment size (303). Namely, the use efficiency of a high-speed memory is optimized, a part where a polygon is present is plotted by using high-speed sequential access, and a pixel write mask is used to determine which pixel is displayed on the screen of a display device by writing it in a pixel grid or frame buffer from the high-speed sequential access memory. Right after the segment size is determined, a segment is written in a high-speed sequential memory such as an SRAM and the segment is stored (305 and 307). Then it is decided whether or not polygon plotting corresponding to a polygon plotting command is completed (309).

12. 发明专利

JPH1097517A PARALLEL MULTIPLICATION INTEGRATING ARRAY CIRCUIT 失效
公开(公告)号：JPH1097517A
公开(公告)日：1998-04-14
申请号：JP17466197
申请日：1997-06-30
申请人： CIRRUS LOGIC INC
发明人： OGLETREE THOMAS
IPC分类号： G06F17/10 , G06F7/544
摘要： PROBLEM TO BE SOLVED: To speed up an operation processing shown by the form of the sum of products by providing a first multiplexer (MUX) giving 2x bit product output and a second multiplexer having output supplying one calculated value. SOLUTION: An inner control circuit 380 receives a discrete operation control value and a BM state control signal from BMMC devices 310-315. The inner control circuit 380 selects i-th input of first MUX 320 corresponding to a booth multiplier BMi by using a first MUX selection bus 382. A PMAA circuit 200 contains second MUX 370. Second MUX 370 has m=four inputs and respective inputs are connected to receive an output signal from one of four accumulator registers 360-363. An outer controller controls the selection bus 371 of second MUX 370 so that the output of ACCI being one of the accumulator registers 360-363 is selected and supplied j-th input of second MUX 370 is selected, and it is outputted through second MUX 370.

13. 发明专利

JPH1083337A MEMORY, INTEGRATED CIRCUIT AND METHOD FOR OPERATING MEMORY 失效
公开(公告)号：JPH1083337A
公开(公告)日：1998-03-31
申请号：JP15900597
申请日：1997-06-16
申请人： CIRRUS LOGIC INC
发明人： RAO MOHAN G R
IPC分类号： G11C11/41 , G06F12/00 , G11C7/10
摘要： PROBLEM TO BE SOLVED: To optimize access through a data port. SOLUTION: This memory is provided with first and second memory banks 201a and 201b and plural data input/output terminals. A first sub-set among the plural data input/output terminals is for accessing the first memory bank 201a and a second sub-set among the plural data input/output terminals is for accessing the second memory bank 201b.

14. 发明专利

JPH1074387A MEMORY, MEMORY SYSTEM AND METHOD FOR MAPPING MEMORY DEVICE 失效
公开(公告)号：JPH1074387A
公开(公告)日：1998-03-17
申请号：JP10023397
申请日：1997-04-17
申请人： CIRRUS LOGIC INC
发明人： TAYLOR RONALD , SHARMA SUDHIR , RUNAS MICHAEL E
IPC分类号： G11C11/401 , G06F12/02 , G06F12/06 , G11C5/06
摘要： PROBLEM TO BE SOLVED: To provide a memory device of wide range containing a DRAW memory device of wide range. SOLUTION: A memory 600 is provided with an array constituted of plural memory cells 201, plural input/output terminals which receive control bits during a control cycle and perform access to some cells selected from plural cells 201 during a data access cycle. Further, a command bit input terminal 221 is provided in order to receive a command bit and to start the control cycle and a mapping input terminal 222 is provided in order to receive a mapping enable signal and to start a mapping mode. Circuits 215/216 are provided to enable mapping an address set for performing access to the cells 201 of the array by decoding the control bit received during at least one control cycles generated in the mapping mode.

15. 发明专利

JPH1032493A METHOD AND DEVICE FOR PROCESSING DIGITAL SIGNAL 失效
公开(公告)号：JPH1032493A
公开(公告)日：1998-02-03
申请号：JP5674497
申请日：1997-03-11
申请人： CIRRUS LOGIC INC
发明人： WELLAND DAVID R
IPC分类号： H03H17/00 , G06F7/72 , H03M7/18
摘要： PROBLEM TO BE SOLVED: To reduce power by means of reducing the load of a signal active level and a signal line by processing a digital signal in a one hot RNS system obtained by means of combining an RNS system and a one hot scheme. SOLUTION: For adding the RNS digits of two numbers, the voltage signal of the line 1 of an addend A and the of the line 2 of an addend are set to be high and the voltage signals of the other lines are set to be low. Switches SW2, 6 and 7 are turned on by the voltage of the line 2 of the addend B. The other switches are turned off. The voltage of the line 1 of the addend A is connected to the line 0 of SUM. Furthermore, the voltage of the line 2 of the addend A is connected to the line 1 of SUM. The voltage of the line 0 of the addend A is connected to the line 2 of SUM. Thus, only the line 0 becomes high in the lines 0, 1 and 2 of X3 in SUM, and it corresponds to a sum 12 (025RNS). Thus, high speed by the RUM system can be realized and the load of the signal active level and that of the signal line reduce.

17. 发明专利

JP6545707B2 切換可能な2次再生経路有权
公开(公告)号：JP6545707B2
公开(公告)日：2019-07-17
申请号：JP2016562946
申请日：2015-04-10
申请人：シーラスロジック,インコーポレイテッド , Cirrus Logic,Inc.
发明人：ダス、テヤスヴィ , メランソン、ジョンエル. , タッカー、ジョン、シー. , フェイ、シャオファン
IPC分类号： H03M3/02 , H03M1/68

18. 发明专利

JP2018502324A フィードバック適応ノイズ消去の性能および安定性制御のための回路および方法审中-公开
公开(公告)号：JP2018502324A
公开(公告)日：2018-01-25
申请号：JP2017533333
申请日：2015-12-17
申请人：シーラスロジック,インコーポレイテッド , Cirrus Logic,Inc.
发明人：ルー、ヤン , チョウ、デイヨン , ミラー、アントニオジェイ. , リ、ニン
IPC分类号： G10K11/178
CPC分类号： G10K11/178 , G10K11/17833 , G10K11/17875 , G10K11/17881 , G10K2210/1081 , G10K2210/3056 , G10K2210/503 , G10K2210/506 , H04R1/1083 , H04R2460/01
摘要：トランスデューサ付近の周囲のオーディオ音を消去するための方法は、トランスデューサの出力と、トランデューサにおける周囲のオーディオ音とを示す誤差マイクロフォン信号を受信することを含み得る。また、方法は、トランスデューサの音響出力における周囲のオーディオ音の影響を打ち消すためにアンチノイズ信号を生成することであって、誤差マイクロフォン信号に基づきフィードバックアンチノイズ信号を生成する応答を有するフィードバックフィルタを適用することと、フィードバックフィルタと直列に、可変ゲイン要素を適用することとを、含む、アンチノイズ信号を生成することを含み得る。方法は、フィードバックフィルタに、アンチノイズ信号において望ましくない成分を生成させる可能性のある周囲のオーディオ事象が起こっているかをモニタし、望ましくない成分を低減するように、可変ゲイン要素のゲインを制御することをさらに含み得る。

19. 发明专利

JP2010045865A Adaptive dead time control for push-pull switching circuit 审中-公开
标题翻译：用于推拉开关电路的自适应死时间控制
公开(公告)号：JP2010045865A
公开(公告)日：2010-02-25
申请号：JP2009266866
申请日：2009-11-24
申请人： Cirrus Logic Inc , シーラスロジック,インコーポレイテッドCirrus Logic,Inc.
发明人： MELANSON JOHN LAURENCE
IPC分类号： H03K17/16 , H03K17/687 , H03F1/32 , H03F3/217 , H03K5/151 , H03K17/92 , H03K19/00 , H03K19/0175 , H03K19/0185 , H03K19/0948
CPC分类号： H03F1/32 , H03F3/2171 , H03K5/1515 , H03K19/0013 , H03K19/018585
摘要： PROBLEM TO BE SOLVED: To adaptively reduce dead time in a switching circuit (305).
SOLUTION: An apparatus for adaptively reducing dead time in a switching circuit includes: overlap detection circuitry (310) for measuring (406) the dead time/overlap of switches (104, 105); and control circuitry (320) for setting (408) the dead time to the optimum level (407) (generally the minimum possible dead time without any overlap occurring). The dead time/overlap may be detected by measuring the current through switches (501), the current into a power supply (601), the voltage waveform (710, 711, 712) at the switch point, or the average voltage waveform (803) at the switch point. The dead time may be controlled by utilizing delay elements (902, 903) prior to drivers (302, 303) or by utilizing circuitry (302a/320b) to control the driver timing.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：自适应地减少开关电路（305）中的死区时间。解决方案：用于自适应地减少开关电路中的死区时间的装置包括：重叠检测电路（310），用于测量（406）开关（104,105）的死区时间/重叠; 以及控制电路（320），用于将死区时间设置为（408）至最佳电平（407）（通常为最小可能的死区时间而不发生任何重叠）。死区时间/重叠可以通过测量通过开关（501）的电流，到电源（601）的电流，开关点处的电压波形（710,711,712）或平均电压波形（803 ）在切换点。可以通过在驱动器（302,303）之前利用延迟元件（902,903）或利用电路（302a / 320b）来控制驱动器时序来控制死区时间。版权所有（C）2010，JPO＆INPIT

20. 发明专利

JP2009004095A Optical disk drive storage system, method for controlling movement of optical lead head, and sliding mode controller 审中-公开
标题翻译：光盘驱动器存储系统，控制光头运动的方法和滑模控制器
公开(公告)号：JP2009004095A
公开(公告)日：2009-01-08
申请号：JP2008256797
申请日：2008-10-01
申请人： Cirrus Logic Inc , シーラスロジック,インコーポレイテッドCirrus Logic,Inc.
发明人： SUPINO LOUIS , ROMANO PAUL M , REIFF FRANCIS H
IPC分类号： G11B7/085 , G05B13/02 , G11B7/09
CPC分类号： G11B7/0946 , G05B13/0255 , G11B7/08529 , G11B7/0908
摘要： PROBLEM TO BE SOLVED: To provide an optical disk drive servo control system in which sensitivity to a change in parameter is not so high, and transition can be controlled more favorably and the implementing cost of a complex adaptive linear controller is eliminated.
SOLUTION: The optical disk storage system is provided with a sliding mode controller for actuating an optical lead head assembly on an optical disk during focus capturing, focus tracking, track seeking and centerline tracking. The sliding mode controller operates by switching feedback between a positive state and a negative state so as to follow a predetermined phase state track by allocating a certain phase state (e.g., position error or speed of the lead head).
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种光盘驱动器伺服控制系统，其中对参数变化的灵敏度不那么高，并且可以更有利地控制转换，并且消除了复杂的自适应线性控制器的实现成本。解决方案：光盘存储系统设置有滑动模式控制器，用于在聚焦捕获，聚焦跟踪，跟踪寻找和中心线跟踪期间致动光盘上的光引导头组件。滑动模式控制器通过在正状态和负状态之间切换反馈来操作，以便通过分配一定的相位状态（例如，引导头的位置误差或速度）来跟随预定的相位状态轨迹。版权所有（C）2009，JPO＆INPIT

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