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11. 发明申请

US20100309706A1 Load reduced memory module and memory system including the same 有权
标题翻译：负载减少的内存模块和包含相同的内存系统
公开(公告)号：US20100309706A1
公开(公告)日：2010-12-09
申请号：US12801326
申请日：2010-06-03
申请人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
发明人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
IPC分类号： G11C5/02 , G11C7/00
CPC分类号： G11C7/00 , G11C5/02 , G11C5/04 , G11C5/063 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/109 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片，多个数据寄存器缓冲器以及安装在模块PCB上的命令/地址/控制寄存器缓冲器。数据寄存器缓冲器与存储器芯片执行数据传输。命令/地址/控制寄存器缓冲器执行命令/地址/控制信号的缓冲并产生控制信号。缓冲的命令/地址/控制信号被提供给存储器芯片，并且控制信号被提供给数据寄存器缓冲器。根据本发明，由于数据寄存器缓冲器和存储器芯片之间的线路长度被缩短，可以实现相当高的数据传输速率。

12. 发明申请

US20090278459A1 INDUCTION COIL, A PLASMA GENERATOR AND A PLASMA GENERATING METHOD 有权
标题翻译：感应线圈，等离子体发生器和等离子体发生方法
公开(公告)号：US20090278459A1
公开(公告)日：2009-11-12
申请号：US12509434
申请日：2009-07-24
申请人： Georgy K. Vinogradov , Vladimir M. Menagarishvili , Tetsuhiko Shimamura , Masayuki Nakamura
发明人： Georgy K. Vinogradov , Vladimir M. Menagarishvili , Tetsuhiko Shimamura , Masayuki Nakamura
IPC分类号： H05H1/24 , H01F27/29
CPC分类号： H05H1/46 , H01J37/321 , H01J37/3211
摘要： The plasma generator of our invention comprises of the induction coil which is symmetric with respect to the reference plane between two terminal ends. Plasma processing gas is supplied to a predetermined space, and high frequency electricity is supplied to the induction coil, thereby the plasma generator generates plasma in the space. The reference plane passes between the two terminal ends and through longitude axis of the induction coil. The plasma generator can generate plasma with high quality of homogeneous.
摘要翻译：本发明的等离子体发生器包括感应线圈，其相对于两个终端之间的参考平面对称。将等离子体处理气体供给到规定的空间，向感应线圈供给高频电力，等离子体发生器在该空间中产生等离子体。参考平面通过两个终端之间并通过感应线圈的经度轴。等离子体发生器可以产生质量均匀的等离子体。

13. 发明授权

US07609572B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07609572B2
公开(公告)日：2009-10-27
申请号：US11963831
申请日：2007-12-22
申请人： Hiroaki Nakaya , Riichiro Takemura , Satoru Akiyama , Tomonori Sekiguchi , Masayuki Nakamura , Shinichi Miyatake
发明人： Hiroaki Nakaya , Riichiro Takemura , Satoru Akiyama , Tomonori Sekiguchi , Masayuki Nakamura , Shinichi Miyatake
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/08 , G11C2207/005
摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.
摘要翻译：在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低感觉速度增加。因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。

14. 发明申请

US20080273413A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080273413A1
公开(公告)日：2008-11-06
申请号：US12165681
申请日：2008-07-01
申请人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C5/14 , G11C5/147 , G11C7/1072 , G11C8/12 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
摘要翻译：提供了一种同步DRAM，其包括基于DRAM是否处于掉电模式的电源电路的操作的布置。在一个实施例中，提供了第一电源电路和第二电源电路，其接收外部提供的电压并输出内部电源电压。当同步DRAM的半导体器件处于掉电模式时，第一电源电路不工作。然而，第二电源电路在掉电模式期间连续运行。在另一种布置中，基于DRAM是否处于断电模式来控制限压器电路的操作。

15. 发明申请

US20060250876A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060250876A1
公开(公告)日：2006-11-09
申请号：US11483649
申请日：2006-07-11
申请人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
IPC分类号： G11C5/14
CPC分类号： G11C5/063 , G11C5/14 , G11C5/147 , G11C7/1072 , G11C8/12 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
摘要翻译：提供了一种同步DRAM，其包括基于DRAM是否处于掉电模式的电源电路的操作的布置。在一个实施例中，提供了第一电源电路和第二电源电路，其接收外部提供的电压并输出内部电源电压。当同步DRAM的半导体器件处于掉电模式时，第一电源电路不工作。然而，第二电源电路在掉电模式期间连续运行。在另一种布置中，基于DRAM是否处于断电模式来控制限压器电路的操作。

16. 发明申请

US20060119101A1 Pipe having enlarged and reduced diameters, and ejector using thereof 审中-公开
标题翻译：具有放大和缩小直径的管，以及使用其的喷射器
公开(公告)号：US20060119101A1
公开(公告)日：2006-06-08
申请号：US11270255
申请日：2005-11-09
申请人： Yukio Suzuki , Masayuki Nakamura
发明人： Yukio Suzuki , Masayuki Nakamura
IPC分类号： F16L21/00
CPC分类号： F16L9/006 , F25B2341/0012 , F25B2500/01
摘要： A pipe may have enlarged and reduced diameters, which has low costs and which can prevent leakage of a fluid such as a refrigerant from the pipe even in such a configuration that a reduced diameter portion is continuous to an enlarged diameter portion continuous to another reduced diameter portion, the pipe being integrally and continuously formed by plastic or malleable working so as to having outer diameters (D1 . . . D8) which are longitudinally different from one another, and accordingly, the reduced diameter portion (1b-1c) being continuous to the enlarged diameter portion (1c-1d) which is continuous to another reduced diameter portion (1d-1e).
摘要翻译：管道可以具有扩大和减小的直径，其成本低，并且可以防止诸如制冷剂的流体从管道泄漏，即使是直径减小的部分连续到与另一直径相连的扩大直径部分的构造所述管通过塑料或有延展性的工作一体地连续地形成，以具有彼此纵向不同的外径（D1 ... D8），因此，所述直径减小部分（1b-1c）为连续到与另一直径减小部分（1d-1e）连续的扩大直径部分（1c-1d）。

17. 发明申请

US20060070955A1 Method and apparatus for separating a target molecule from a liquid mixture 有权
公开(公告)号：US20060070955A1
公开(公告)日：2006-04-06
申请号：US11241482
申请日：2005-09-30
申请人： Andrew Rabins , Kelly Gibbens , Masayuki Nakamura , Kannan Seshadri , Robert Fitzsimons , Larry Carson , Stephen Larsen
发明人： Andrew Rabins , Kelly Gibbens , Masayuki Nakamura , Kannan Seshadri , Robert Fitzsimons , Larry Carson , Stephen Larsen
IPC分类号： B01D15/08
CPC分类号： B01J20/28033 , B01D15/1828
摘要： A simulated moving bed apparatus and methods are described for continuously separating a target molecule from a liquid mixture, using a simulated moving bed system. The simulated moving bed system includes a plurality of filter cartridge modules in serial fluid communication. Each filter cartridge module includes a volume of stationary phase particulates adjacent a porous substrate layer. Each filter cartridge module also includes recirculation piping in fluid connection with a filter cartridge outlet and a filter cartridge inlet.

18. 发明授权

US07022738B2 α-ketoamide derivative and use thereof 失效
标题翻译： α-酮酰胺衍生物及其用途
公开(公告)号：US07022738B2
公开(公告)日：2006-04-04
申请号：US10521764
申请日：2003-07-11
申请人： Masayuki Nakamura , Jun Inoue
发明人： Masayuki Nakamura , Jun Inoue
IPC分类号： A61K31/18 , A61K38/05 , C07C311/18
CPC分类号： C07C311/19
摘要： The present invention provides a compound represented by the formula (I): wherein R1, R2 and R3 each represents a lower alkyl group.
摘要翻译：本发明提供由式（I）表示的化合物：其中R 1，R 2和R 3各自表示低级烷基。

19. 发明申请

US20050176704A1 Hydroxymorpholinone derivative and medicinal use thereof 失效
标题翻译：羟基吗啉酮衍生物及其医药用途
公开(公告)号：US20050176704A1
公开(公告)日：2005-08-11
申请号：US10509253
申请日：2003-03-27
申请人： Masayuki Nakamura , Jun Inoue
发明人： Masayuki Nakamura , Jun Inoue
IPC分类号： A61K31/5375 , A61P9/00 , A61P9/10 , A61P19/10 , A61P25/00 , A61P25/28 , A61P27/02 , A61P27/06 , A61P27/12 , A61P37/02 , A61P43/00 , C07D265/32 , A61K31/537
CPC分类号： A61K31/5375 , C07D265/32
摘要： A compound represented by the following formula (I) wherein R1 and R2 are each a lower alkyl group optionally having substituents, which has a calpain inhibitory activity, or a salt thereof is provided.
摘要翻译：由下式（I）表示的化合物，其中R 1和R 2各自为任选具有钙蛋白酶抑制活性的取代基的低级烷基或盐提供。

20. 发明授权

US06915476B2 Redundancy semiconductor memory device with error correction code (ECC) circuits for correcting errors in recovery fuse data 失效
标题翻译：具有用于校正恢复熔丝数据中的错误的纠错码（ECC）电路的冗余半导体存储器件
公开(公告)号：US06915476B2
公开(公告)日：2005-07-05
申请号：US11004799
申请日：2004-12-07
申请人： Makoto Morino , Masayuki Nakamura
发明人： Makoto Morino , Masayuki Nakamura
IPC分类号： G11C29/04 , G06F11/10 , G11C7/00 , G11C11/401 , G11C29/00 , G11C29/42
CPC分类号： G06F11/1008 , G11C29/789 , G11C29/802 , G11C29/812
摘要： A semiconductor integrated circuit device includes a memory array having first to Nth banks, where N is an integer greater than or equal to 2. The memory array further includes a redundancy block having first to Nth column recovery circuit blocks corresponding to the first to Nth banks, first to Nth row recovery circuit blocks corresponding to the first to Nth banks, first to Nth ECC fuse blocks corresponding to the first to Nth banks, and first to Nth ECC circuits corresponding to the first to Nth banks. During initial cycles, the first to Nth ECC circuits correct errors in column recovery fuse data in the first to Nth column recovery circuit blocks and errors in row recovery fuse data in the first to Nth row recovery circuit blocks by using ECC fuse data in the first to Nth ECC fuse blocks, respectively.
摘要翻译：半导体集成电路装置包括具有第一至第N个存储体的存储器阵列，其中N是大于或等于2的整数。存储器阵列还包括具有与第一至第N个存储体相对应的第一至第N列恢复电路块的冗余块对应于第一至第N组的第一至第N行恢复电路块，对应于第一至第N个存储体的第一至第N个ECC熔丝块以及对应于第一至第N个存储体的第一至第N个ECC电路。在初始周期期间，第一至第N ECC电路通过在第一至第N行ECC恢复电路块中的第一至第N列恢复电路块中的ECC恢复熔丝数据和第一至第N行恢复电路块中的ECC恢复熔丝数据中的错误来校正第一至第N行恢复电路块中的ECC熔丝数据到第N个ECC保险丝块。

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