专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07851889B2 MOSFET device including a source with alternating P-type and N-type regions 有权
标题翻译： MOSFET器件包括具有交替P型和N型区的源
公开(公告)号：US07851889B2
公开(公告)日：2010-12-14
申请号：US11742363
申请日：2007-04-30
申请人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
发明人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
IPC分类号： H01L21/00
CPC分类号： H01L29/0847 , H01L29/0692 , H01L29/1087 , H01L29/456 , H01L29/7835
摘要： Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body (120) including a surface and a transistor source (300) located in the semiconductor body proximate the surface, and the transistor source includes an area (310) of alternating conductivity regions (3110, 3120). Another apparatus includes a semiconductor body (120) including a first conductivity and a transistor source (500) located in the semiconductor body. The transistor source includes multiple regions (5120) including a second conductivity, wherein the regions and the semiconductor body form an area (510) of alternating regions of the first and second conductivities. One method includes implanting a semiconductor well (120) including a first conductivity in a substrate (110) and implanting a plurality of doped regions (5120) comprising a second conductivity in the semiconductor well. An area (510) comprising regions of alternating conductivities is then formed in the semiconductor well.
摘要翻译：提供了用于制造具有降低的双极效应的半导体器件的装置和方法。一种装置包括半导体本体（120），其包括位于半导体本体附近的表面和晶体管源（300），并且晶体管源包括交替导电区域（3110,3120）的区域（310）。另一种装置包括：半导体本体（120），其包括位于半导体本体中的第一导电性和晶体管源（500）。晶体管源包括包括第二导电性的多个区域（5120），其中所述区域和半导体主体形成第一和第二电导率的交替区域的区域（510）。一种方法包括在衬底（110）中注入包括第一导电性的半导体阱（120），并在半导体阱中注入包含第二导电性的多个掺杂区域（5120）。然后在半导体阱中形成包括交变电导率区域的区域（510）。

12. 发明授权

US07763937B2 Variable resurf semiconductor device and method 有权
标题翻译：可变复用半导体器件及方法
公开(公告)号：US07763937B2
公开(公告)日：2010-07-27
申请号：US11601127
申请日：2006-11-15
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L29/00
CPC分类号： H01L29/063 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Methods and apparatus are provided for semiconductor device (60, 95, 100, 106). The semiconductor device (60, 95, 100, 106), comprises a first region (64, 70) of a first conductivity type extending to a first surface (80), a second region (66) of a second, opposite, conductivity type forming with the first region (70) a first PN junction (65) extending to the first surface (80), a contact region (68) of the second conductivity type in the second region (66) at the first surface (80) and spaced apart from the first PN junction (65) by a first distance (LDS), and a third region (82, 96-98, 108) of the first conductivity type and of a second length (LBR), underlying the second region (66) and forming a second PN junction (63) therewith spaced apart from the first surface (80) and located closer to the first PN junction (65) than to the contact region (68). The breakdown voltage is enhanced without degrading other useful properties of the device (60, 95, 100, 106).
摘要翻译：为半导体器件（60,95,100,106）提供了方法和装置。半导体器件（60,95,100,106）包括延伸到第一表面（80）的第一导电类型的第一区域（64,70），第二相对导电类型的第二区域（66）与所述第一区域（70）形成延伸到所述第一表面（80）的第一PN结（65），在所述第一表面（80）处的所述第二区域（66）中的所述第二导电类型的接触区域（68）与第一PN结（65）间隔开第一距离（LDS），以及第二导电类型和第二长度（LBR）的第三区域（82,96-98,108），位于第二区域并且与第一表面（80）间隔开并且位于比接触区域（68）更靠近第一PN结（65）的位置处形成第二PN结（63）。提高击穿电压，而不会降低器件（60,95,100,106）的其他有用特性。

13. 发明授权

US07436025B2 Termination structures for super junction devices 有权
标题翻译：超连接器件的端接结构
公开(公告)号：US07436025B2
公开(公告)日：2008-10-14
申请号：US11540770
申请日：2006-09-29
申请人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
发明人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
IPC分类号： H01L29/76
CPC分类号： H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/1045 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device 10 is provided. A first layer 12 has a first dopant type; a second layer 14 is provided over the first layer 12; and a third layer 16 is provided over the second layer and has the first dopant type. A plurality of first and second semiconductor regions 22, 24 are within the third layer. The first semiconductor region 22 has the first dopant type, and the second semiconductor region 24 has the second dopant type. The first and second semiconductor regions 22, 24 are disposed laterally to one another in an alternating pattern to form a super junction, and the super junction terminates with a final second semiconductor region 24, 24′ of the second dopant type.
摘要翻译：提供半导体器件10。第一层12具有第一掺杂剂类型; 在第一层12上设置第二层14; 并且第三层16设置在第二层上并且具有第一掺杂剂类型。多个第一和第二半导体区域22,24在第三层内。第一半导体区域22具有第一掺杂剂类型，第二半导体区域24具有第二掺杂剂类型。第一和第二半导体区域22,24以交替图案彼此横向地设置以形成超结，并且超结终止于第二掺杂剂类型的最终第二半导体区域24,24'。

14. 发明授权

US07820519B2 Process of forming an electronic device including a conductive structure extending through a buried insulating layer 有权
标题翻译：形成包括延伸穿过掩埋绝缘层的导电结构的电子器件的工艺
公开(公告)号：US07820519B2
公开(公告)日：2010-10-26
申请号：US11556544
申请日：2006-11-03
申请人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang , Van Wong
发明人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang , Van Wong
IPC分类号： H01L21/331
CPC分类号： H01L21/84 , H01L21/823481 , H01L21/823878 , H01L27/0617 , H01L27/08 , H01L27/088 , H01L27/1203
摘要： A process of forming an electronic device can include providing a semiconductor-on-insulator substrate including a substrate, a first semiconductor layer, and a buried insulating layer lying between the first semiconductor layer and the substrate. The process can also include forming a field isolation region within the semiconductor layer, and forming an opening extending through the semiconductor layer and the buried insulating layer to expose the substrate. The process can further include forming a conductive structure within the opening, wherein the conductive structure abuts the substrate.
摘要翻译：形成电子器件的工艺可以包括提供绝缘体上半导体衬底，其包括位于第一半导体层和衬底之间的衬底，第一半导体层和掩埋绝缘层。该工艺还可以包括在半导体层内形成场隔离区域，以及形成延伸穿过半导体层和掩埋绝缘层的开口以露出衬底。该方法还可以包括在开口内形成导电结构，其中导电结构邻接衬底。

15. 发明授权

US07777257B2 Bipolar Schottky diode and method 有权
标题翻译：双极肖特基二极管及方法
公开(公告)号：US07777257B2
公开(公告)日：2010-08-17
申请号：US11674886
申请日：2007-02-14
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L29/317 , H01L21/42
CPC分类号： H01L29/872 , H01L29/0634 , H01L29/402 , H01L29/456 , H01L29/47 , H01L29/66143
摘要： A low leakage bipolar Schottky diode (20, 40, 87) is formed by parallel lightly doped N (32, 52, 103) and P (22, 42, 100) regions adapted to form superjunction regions. First ends of the P regions (22, 42, 100) are terminated by P+ layers (21, 41, 121) and second, opposed ends of the N regions (32, 52, 103) are terminated by N+ layers (31, 51, 131). Silicide layers (24, 34, 44, 54, 134, 124) are provided in contact with both ends of the parallel N and P regions (22, 32, 42, 52, 100, 103), thereby forming at the first end ohmic contacts (28, 48) with the P+ regions (21, 41, 121) and Schottky contacts (37, 57) with the N regions 32, 52, 103) and at the second, opposite end, ohmic contacts (38, 58) with the N+ regions (31, 51, 131) and Schottky contacts (27, 47) with the P regions (22, 42, 100). When forward biased current flows in both N (32, 52) and P (22, 42) regions thereby reducing the forward drop. When reverse biased, a substantial portion of the voltage is dropped across the lightly doped N (32, 52) and P (22, 42) superjunction regions, thereby significantly reducing the reverse leakage.
摘要翻译：通过平行轻掺杂N（32,52,103）和适于形成超结区的P（22,42,100）区域形成低漏极双极肖特基二极管（20,40,87）。 P区域（22,42,100）的第一端由P +层（21,41,121）端接，并且N区域（32,52,103）的相对端由N +层（31,51 ，131）。提供与平行N和P区（22,32,42,52,100,103）的两端接触的硅化物层（24,34,44,54,134,124），从而在第一端形成欧姆具有P +区域（21,41,121）的触点（28,48）和具有N个区域32,52,103的肖特基触头（37,57）），并且在第二相对端，欧姆接触件（38,58）与P区（22,42,100）的N +区（31,51,131）和肖特基接触（27,47）。当正向偏置电流在N（32,52）和P（22,42）区域中流动时，从而减少向下的下降。当反向偏置时，电压的大部分在轻掺杂的N（32,52）和P（22,42）超结区域下降，从而显着减少反向泄漏。

16. 发明授权

US07723204B2 Semiconductor device with a multi-plate isolation structure 有权
标题翻译：具有多板隔离结构的半导体器件
公开(公告)号：US07723204B2
公开(公告)日：2010-05-25
申请号：US11390918
申请日：2006-03-27
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/763 , H01L21/764 , H01L21/823481
摘要： A microelectronic assembly and a method for constructing a microelectronic assembly are provided. The microelectronic assembly may include a semiconductor substrate with an isolation trench (62) formed therein. The isolation trench (62) may have first and second opposing inner walls (74, 76) and a floor (78). First and second conductive plates (106) may be formed over the first and second opposing inner walls (74, 76) of the isolation trench (62) respectively such that there is a gap (90) between the first and second conductive plates (106). First and second semiconductor devices (114) may be formed in the semiconductor substrate on opposing sides of the isolation trench (62). The method may include forming a trench (62) in a semiconductor substrate, forming first and second conductive plates (106) within the trench, and forming first and second semiconductor devices (114) in the semiconductor substrate on opposing sides of the trench (62).
摘要翻译：提供微电子组件和构造微电子组件的方法。微电子组件可以包括其中形成有隔离沟槽（62）的半导体衬底。隔离沟槽（62）可以具有第一和第二相对的内壁（74,76）和底板（78）。第一和第二导电板（106）可以分别形成在隔离沟槽（62）的第一和第二相对的内壁（74,76）上，使得在第一和第二导电板（106）之间存在间隙（90））。可以在隔离沟槽（62）的相对侧上的半导体衬底中形成第一和第二半导体器件（114）。该方法可以包括在半导体衬底中形成沟槽（62），在沟槽内形成第一和第二导电板（106），并且在沟槽（62）的相对侧上的半导体衬底中形成第一和第二半导体器件（114））。

17. 发明授权

US07511319B2 Methods and apparatus for a stepped-drift MOSFET 有权
标题翻译：梯形漂移MOSFET的方法和装置
公开(公告)号：US07511319B2
公开(公告)日：2009-03-31
申请号：US11361624
申请日：2006-02-24
申请人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
发明人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
IPC分类号： H01L21/76
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/1083 , H01L29/456 , H01L29/66659 , H01L29/66681 , H01L29/7816
摘要： A power metal-oxide-semiconductor field effect transistor (MOSFET)(100) incorporates a stepped drift region including a shallow trench insulator (STI)(112) partially overlapped by the gate (114) and which extends a portion of the distance to a drain region (122). A silicide block extends from and partially overlaps STI (112) and drain region (122). The STI (112) has a width that is approximately 50% to 75% of the drift region.
摘要翻译：功率金属氧化物半导体场效应晶体管（MOSFET）（100）包括阶梯状漂移区域，其包括与栅极（114）部分重叠的浅沟槽绝缘体（112），并将距离的一部分延伸到漏区（122）。硅化物块从STI（112）和漏极区（122）延伸并部分重叠。 STI（112）的宽度为漂移区域的大约50％至75％。

18. 发明申请

US20080191305A1 BIPOLAR SCHOTTKY DIODE AND METHOD 有权
标题翻译：双极肖特基二极管和方法
公开(公告)号：US20080191305A1
公开(公告)日：2008-08-14
申请号：US11674886
申请日：2007-02-14
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L29/861 , H01L21/283
CPC分类号： H01L29/872 , H01L29/0634 , H01L29/402 , H01L29/456 , H01L29/47 , H01L29/66143
摘要： A low leakage bipolar Schottky diode (20, 40, 87) is formed by parallel lightly doped N (32, 52, 103) and P (22, 42, 100) regions adapted to form superjunction regions. First ends of the P regions (22, 42, 100) are terminated by P+ layers (21, 41, 121) and second, opposed ends of the N regions (32, 52, 103) are terminated by N+ layers (31, 51, 131). Silicide layers (24, 34, 44, 54, 134, 124) are provided in contact with both ends of the parallel N and P regions (22, 32, 42, 52, 100, 103), thereby forming at the first end ohmic contacts (28, 48) with the P+ regions (21, 41, 121) and Schottky contacts (37, 57) with the N regions 32, 52, 103) and at the second, opposite end, ohmic contacts (38, 58) with the N+ regions (31, 51, 131) and Schottky contacts (27, 47) with the P regions (22, 42, 100). When forward biased current flows in both N (32, 52) and P (22, 42) regions thereby reducing the forward drop. When reverse biased, a substantial portion of the voltage is dropped across the lightly doped N (32, 52) and P (22, 42) superjunction regions, thereby significantly reducing the reverse leakage.
摘要翻译：通过平行轻掺杂N（32,52,103）和适于形成超结区的P（22,42,100）区域形成低漏极双极肖特基二极管（20,40,87）。 P区域（22,42,100）的第一端由P +层（21,41,121）端接，并且N区域（32,52,103）的相对端由N +层（31,51 ，131）。提供与平行N和P区（22,32,42,52,100,103）的两端接触的硅化物层（24,34,44,54,134,124），从而在第一端形成欧姆具有P +区域（21,41,121）的触点（28,48）和具有N个区域32,52,103的肖特基触头（37,57）），并且在第二相对端，欧姆接触件（38,58）与P区（22,42,100）的N +区（31,51,131）和肖特基接触（27,47）。当正向偏置电流在N（32,52）和P（22,42）区域中流动时，从而减少向下的下降。当反向偏置时，电压的大部分在轻掺杂的N（32,52）和P（22,42）超结区域下降，从而显着减少反向泄漏。

19. 发明申请

US20080191275A1 DOTTED CHANNEL MOSFET AND METHOD 有权
标题翻译： DOTTED CHANNEL MOSFET和方法
公开(公告)号：US20080191275A1
公开(公告)日：2008-08-14
申请号：US11674888
申请日：2007-02-14
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0692 , H01L29/1045 , H01L29/1087 , H01L29/4238 , H01L29/66659 , H01L29/78
摘要： A improved MOSFET (50, 51, 75, 215) has a source (60) and drain (62) in a semiconductor body (56), surmounted by an insulated control gate (66) located over the body (56) between the source (60) and drain (62) and adapted to control a conductive channel (55) extending between the source (60) and drain (62). The insulated gate (66) is perforated by a series of openings (61) through which highly doped regions (69) in the form of a series of (e.g., square) dots (69) of the same conductivity type as the body (56) are provided, located in the channel (55), spaced apart from each other and from the source (60) and drain (62). These channel dots (69) are desirably electrically coupled to a highly doped contact (64) to the body (56). The resulting device (50, 51, 75, 215) has a greater SOA, higher breakdown voltage and higher HBM stress resistance than equivalent prior art devices (20) without the dotted channel. Threshold voltage is not affected.
摘要翻译：改进的MOSFET（50,51,75,215）在半导体本体（56）中具有源极（60）和漏极（62），其被位于源极（56）之间的绝缘控制栅极（66）所覆盖，（60）和漏极（62），并且适于控制在源极（60）和漏极（62）之间延伸的导电通道（55）。绝缘栅极（66）由一系列开口（61）穿孔，通过该开口（61），与体（56）相同导电类型的一系列（例如，正方形）点（69）形式的高度掺杂区域（69）穿过该开口）设置在通道（55）中，彼此间隔开并且与源（60）和排水口（62）间隔开。这些通道点（69）期望地电耦合到主体（56）的高度掺杂的触点（64）。所得到的器件（50,51,75,215）具有比没有点通道的等效现有技术器件（20）更大的SOA，更高的击穿电压和更高的HBM应力电阻。阈值电压不受影响。

20. 发明申请

US20100230736A1 High Voltage Deep Trench Capacitor 有权
标题翻译：高压深沟槽电容器
公开(公告)号：US20100230736A1
公开(公告)日：2010-09-16
申请号：US12791996
申请日：2010-06-02
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L27/108
CPC分类号： H01L29/94 , H01L27/13 , H01L28/91 , H01L29/66181
摘要： A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).
摘要翻译：半导体工艺和装置提供集成在集成电路中的单独或与边缘电容器（5）对准的高电压深沟槽电容器结构（10）。深沟槽电容器结构由由掺杂的n型SOI半导体层（例如4a-c）形成的第一电容器板（4）构成。第二电容器板（3）由连接到下面的衬底（1）的掺杂p型多晶硅层（3a）形成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式